Thumb2 Backend: 16-bit instruction encoding helper methods

src/arm/constants-arm.h

Index: src/arm/constants-arm.h
diff --git a/src/arm/constants-arm.h b/src/arm/constants-arm.h
index 703613932cd064f34dbf5773acdb4acd3daf43d4..7b79ccd42fa996c9aa6617ac1fcba88bfe9a98ba 100644
--- a/src/arm/constants-arm.h
+++ b/src/arm/constants-arm.h
@@ -142,7 +142,7 @@ inline Condition ReverseCondition(Condition cond) {
 // Instruction objects are pointers to 32bit values, and provide methods to
 // access the various ISA fields.
 typedef int32_t Instr;
-
+typedef int16_t Instr16;

[rmcilroy_google, 2013/09/17 17:28:16]

Add a comment, as per the comment for Instr above.  Also, when you add 32bit
thumb instructions, it would probably be good to seperate them from Instr above,
so maybe name this Thumb2Instr16 and have a Thumb2Instr32 for 32 bit thumb
instructions?

 
 // Opcodes for Data-processing instructions (instructions with a type 0 and 1)
 // as defined in section A3.4
@@ -166,6 +166,94 @@ enum Opcode {
 };
 
 
+// NOTE: these are opcode or opB
+enum ThumbMode1Opcode16 {

[rmcilroy_google, 2013/09/17 17:28:16]

I'm not keen on having these multiple enums for different "modes" of Thumb
instructions. As far as I can see, the regular arm Opcode enum is only used for
disassembly, not code generation.  Can you get away with merging these emums and
merging multiple different types of the same instruction (e.g., ADD_REG_1,
ADD_IMM_1, ADD_IMM_2, ADD_REG_2) 
into a single ADD opcode, with methods on an Instr16 to disambiguate the source
and destination location types?

+  ADD_REG_1 = 3 << 2,
+  ADD_IMM_1 = 7 << 1,
+  ADD_IMM_2 = 3 << 3,
+  SUB_REG = 13,
+  SUB_IMM_1 = 15,
+  SUB_IMM_2 = 7 << 2,
+  MOV_IMM = 4 << 2,
+  CMP_IMM = 5 << 2,
+  LSL_IMM = 0,
+  LSR_IMM = 4,
+  ROR_IMM = 3 << 2,
+  RRX_IMM = 3 << 2,
+  ASR_IMM = 8
+};
+
+
+// NOTE: these are opcodes
+enum ThumbMode2Opcode16 {
+  CMP_REG_1 = 10,
+  AND_REG = 0,
+  EOR_REG = 1,
+  LSL_REG = 2,
+  LSR_REG = 3,
+  ASR_REG = 4,
+  ADC_REG = 5,
+  SBC_REG = 6,
+  ROR_REG = 7,
+  TST_REG = 8,
+  RSB_IMM = 9,
+  CMN_REG = 11,
+  ORR_REG = 12,
+  MUL_REG = 13,
+  BIC_REG = 14,
+  MVN_REG = 15
+};
+
+
+// NOTE: these are opcodes
+enum ThumbMode3Opcode16 {
+  ADD_REG_2 = 0,
+  CMP_REG_2 = 4,
+  MOV_REG_1 = 8,
+  MOV_REG_2 = 0,  // all zeros - so do not call mode function
+  BX_REG = 12,
+  BLX_REG = 14
+};
+
+
+// NOTE: for mode_4 these are opB codes
+enum ThumbMode4_1Opcode16 {
+  STR_REG = 0,
+  STRH_REG = 1,
+  STRB_REG = 2,
+  LDR_REG_1 = 4,
+  LDR_REG_2 = 4,
+  LDRH_REG = 5,
+  LDRB_REG = 6,
+  LDRSB_REG = 3,
+  LDRSH_REG = 7
+};
+
+
+enum ThumbMode4_2Opcode16 {
+  LDR_IMM_1 = 4,
+  STR_IMM_1 = 0
+};
+
+
+enum ThumbMode4_3Opcode16 {
+  LDRB_IMM = 4,
+  STRB_IMM = 0
+};
+
+
+enum ThumbMode4_4Opcode16 {
+  LDRH_IMM = 4,
+  STRH_IMM = 0
+};
+
+
+enum ThumbMode4_5Opcode16 {
+  LDR_IMM_2 = 4,
+  STR_IMM_2 = 0
+};
+
+
 // The bits for bit 7-4 for some type 0 miscellaneous instructions.
 enum MiscInstructionsBits74 {
   // With bits 22-21 01.
@@ -193,13 +281,19 @@ enum {
   P   = 1 << 24,  // Offset/pre-indexed addressing (or post-indexed addressing).
   I   = 1 << 25,  // Immediate shifter operand (or not).
 
+  B3  = 1 << 3,
   B4  = 1 << 4,
   B5  = 1 << 5,
   B6  = 1 << 6,
   B7  = 1 << 7,
   B8  = 1 << 8,
   B9  = 1 << 9,
+  B10 = 1 << 10,
+  B11 = 1 << 11,
   B12 = 1 << 12,
+  B13 = 1 << 13,
+  B14 = 1 << 14,
+  B15 = 1 << 15,
   B16 = 1 << 16,
   B18 = 1 << 18,
   B19 = 1 << 19,