Thumb2 Backend: 16-bit instruction encoding helper methods

src/arm/constants-arm.h

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 124 matching lines @@
 
 
 // -----------------------------------------------------------------------------
 // Instructions encoding.
 
 // Instr is merely used by the Assembler to distinguish 32bit integers
 // representing instructions from usual 32 bit values.
 // Instruction objects are pointers to 32bit values, and provide methods to
 // access the various ISA fields.
 typedef int32_t Instr;
-
+typedef int16_t Instr16;
 
 // Opcodes for Data-processing instructions (instructions with a type 0 and 1)
 // as defined in section A3.4
 enum Opcode {
   AND =  0 << 21,  // Logical AND.
   EOR =  1 << 21,  // Logical Exclusive OR.
   SUB =  2 << 21,  // Subtract.
   RSB =  3 << 21,  // Reverse Subtract.
   ADD =  4 << 21,  // Add.
   ADC =  5 << 21,  // Add with Carry.
   SBC =  6 << 21,  // Subtract with Carry.
   RSC =  7 << 21,  // Reverse Subtract with Carry.
   TST =  8 << 21,  // Test.
   TEQ =  9 << 21,  // Test Equivalence.
   CMP = 10 << 21,  // Compare.
   CMN = 11 << 21,  // Compare Negated.
   ORR = 12 << 21,  // Logical (inclusive) OR.
   MOV = 13 << 21,  // Move.
   BIC = 14 << 21,  // Bit Clear.
   MVN = 15 << 21   // Move Not.
 };
 
 
+// NOTE: these are opcode or opB
+enum ThumbMode1Opcode16 {
+  ADD_REG_1 = 3 << 2,
+  ADD_IMM_1 = 7 << 1,
+  ADD_IMM_2 = 3 << 3,
+  SUB_REG = 13,
+  SUB_IMM_1 = 15,
+  SUB_IMM_2 = 7 << 2,
+  MOV_IMM = 4 << 2,
+  CMP_IMM = 5 << 2,
+  LSL_IMM = 0,
+  LSR_IMM = 4,
+  ROR_IMM = 3 << 2,
+  RRX_IMM = 3 << 2,
+  ASR_IMM = 8
+};
+
+
+// NOTE: these are opcodes
+enum ThumbMode2Opcode16 {
+  CMP_REG_1 = 10,
+  AND_REG = 0,
+  EOR_REG = 1,
+  LSL_REG = 2,
+  LSR_REG = 3,
+  ASR_REG = 4,
+  ADC_REG = 5,
+  SBC_REG = 6,
+  ROR_REG = 7,
+  TST_REG = 8,
+  RSB_IMM = 9,
+  CMN_REG = 11,
+  ORR_REG = 12,
+  MUL_REG = 13,
+  BIC_REG = 14,
+  MVN_REG = 15
+};
+
+
+// NOTE: these are opcodes
+enum ThumbMode3Opcode16 {
+  ADD_REG_2 = 0,
+  CMP_REG_2 = 4,
+  MOV_REG_1 = 8,
+  MOV_REG_2 = 0,  // all zeros - so do not call mode function
+  BX_REG = 12,
+  BLX_REG = 14
+};
+
+
+// NOTE: for mode_4 these are opB codes
+enum ThumbMode4_1Opcode16 {
+  STR_REG = 0,
+  STRH_REG = 1,
+  STRB_REG = 2,
+  LDR_REG_1 = 4,
+  LDR_REG_2 = 4,
+  LDRH_REG = 5,
+  LDRB_REG = 6,
+  LDRSB_REG = 3,
+  LDRSH_REG = 7
+};
+
+
+enum ThumbMode4_2Opcode16 {
+  LDR_IMM_1 = 4,
+  STR_IMM_1 = 0
+};
+
+
+enum ThumbMode4_3Opcode16 {
+  LDRB_IMM = 4,
+  STRB_IMM = 0
+};
+
+
+enum ThumbMode4_4Opcode16 {
+  LDRH_IMM = 4,
+  STRH_IMM = 0
+};
+
+
+enum ThumbMode4_5Opcode16 {
+  LDR_IMM_2 = 4,
+  STR_IMM_2 = 0
+};
+
+
 // The bits for bit 7-4 for some type 0 miscellaneous instructions.
 enum MiscInstructionsBits74 {
   // With bits 22-21 01.
   BX   =  1 << 4,
   BXJ  =  2 << 4,
   BLX  =  3 << 4,
   BKPT =  7 << 4,
 
   // With bits 22-21 11.
   CLZ  =  1 << 4
 };
 
 
 // Instruction encoding bits and masks.
 enum {
   H   = 1 << 5,   // Halfword (or byte).
   S6  = 1 << 6,   // Signed (or unsigned).
   L   = 1 << 20,  // Load (or store).
   S   = 1 << 20,  // Set condition code (or leave unchanged).
   W   = 1 << 21,  // Writeback base register (or leave unchanged).
   A   = 1 << 21,  // Accumulate in multiply instruction (or not).
   B   = 1 << 22,  // Unsigned byte (or word).
   N   = 1 << 22,  // Long (or short).
   U   = 1 << 23,  // Positive (or negative) offset/index.
   P   = 1 << 24,  // Offset/pre-indexed addressing (or post-indexed addressing).
   I   = 1 << 25,  // Immediate shifter operand (or not).
 
+  B3  = 1 << 3,
   B4  = 1 << 4,
   B5  = 1 << 5,
   B6  = 1 << 6,
   B7  = 1 << 7,
   B8  = 1 << 8,
   B9  = 1 << 9,
+  B10 = 1 << 10,
+  B11 = 1 << 11,
   B12 = 1 << 12,
+  B13 = 1 << 13,
+  B14 = 1 << 14,
+  B15 = 1 << 15,
   B16 = 1 << 16,
   B18 = 1 << 18,
   B19 = 1 << 19,
   B20 = 1 << 20,
   B21 = 1 << 21,
   B22 = 1 << 22,
   B23 = 1 << 23,
   B24 = 1 << 24,
   B25 = 1 << 25,
   B26 = 1 << 26,
@@ skipping 548 matching lines @@
   static int Number(const char* name, bool* is_double);
 
  private:
   static const char* names_[kNumVFPRegisters];
 };
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM_CONSTANTS_ARM_H_