Thumb2 Backend: 16-bit instruction encoding helper methods

src/arm/assembler-thumb16.cc

+// Copyright 2012 the V8 project authors. All rights reserved.

[rmcilroy_google, 2013/09/17 17:28:16]

2013

[rkrithiv, 2013/09/27 21:40:49]

Done.

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+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "v8.h"
+
+#if defined(V8_TARGET_ARCH_ARM)
+
+#include "arm/assembler-arm-inl.h"
+#include "serialize.h"
+
+namespace v8 {
+namespace internal {

[rmcilroy_google, 2013/09/17 17:28:16]

I'm not sure whether this should be a separate file from assembler-arm.cc given
that it adds functionality to the Assembler class. However, I do think we should
partition the thumb2 and arm ISA assembler code.  What would be the implications
of separating this out into a separate AssemblerThumb2 class which extends
AssemblerBase?  I'm not sure how this would work with later patches where you
actually start using thumb instructions in the macro-assembler/codegen, but I
think something like this might be cleaner in the end.  One way to do this might
be to change MacroAssembler to inherit from an abstract Assembler (rather than
the concrete Arm ISA assembler as now), and delegate the actual functionality to
either a AssemblerArm or AssemblerThumb2 depending on the mode it is in. Any
thoughts on this from other folks?

In any case, if it remains a seperate file I think it should be renamed
assembler-thumb2.cc (I see in later patches you create an assembler-thumb32.cc
file, but I think this is unecessary and all thumb code, whether for 32 or 16
bit instructions should be together).

[rkrithiv, 2013/09/27 21:40:49]

I agree that having separate AssemblerARM and AssemblerThumb2 would make the
implementation a lot cleaner. This should not be too difficult to get working
with the changes to macro-assembler/codegen for Thumb2.
Could you elaborate on this idea? One thing to remember is that some Assembler
encoding methods (for VFP/SIMD instructions) are common betweeen ARM and Thumb2
modes. We could have a common Assembler class (which would inherit from
AssemblerBase) define the common encoding methods, then have the AssemblerARM
and AssemblerThumb2 classes inherit from the common Assembler class and define
the other encoding methods. And finally we could have a templatized
MacroAssembler class that inherits from either the AssemblerARM or
AssemblerThumb2 based on the mode. There are multiple ways in which we could
separate the two Assemblers, please let me know what design you think would work
best for this.

 
Sure if we decide to keep a single Assembler for ARM and Thumb2, I can refactor
the code in this manner.

[rmcilroy, 2013/10/01 10:26:04]

My thoughts were along the same lines as yours.  Something like a
AssemblerCommon (with the common VFP/SIMD instructions, and abstract / pure
virtual methods for the common instructions). AssemblerArm and AssemblerThumb2
would extend this common class, and add their implementations of these
instructions. I wasn't thinking of templatizing MacroAssembler, I was simply
thinking the the MacroAssembler class would no longer extend any Assembler
class, but would simply create either an AssemblerArm or AssemblerThumb2 object,
and delegate all instruction generation methods to this object.  I'd like some
of the other reviewers to comment on this though, since there is a potential
performance cost to the extra level of indirection, and it would also involve
creating a bunch of methods in macroassembler.cc for the non-macro assembler
methods which simply delegate the call through to the actual underlying
assembler.

Daniel, Ulan, Benedikt, do you guys have any opinion on this?

+
+// A.6.2.1 -> mode1
+Instr16 Assembler::thumb16_mode1(ThumbMode1Opcode16 op) {
+  return (op*B9);
+}
+
+
+// A.6.2.2 -> mode2
+Instr16 Assembler::thumb16_mode2(ThumbMode2Opcode16 op) {
+  return (B14 | op*B6);
+}
+
+
+// A.6.2.3 -> mode3
+Instr16 Assembler::thumb16_mode3(ThumbMode3Opcode16 op) {
+  return (B14 | B10 | op*B6);
+}
+
+
+// A.6.2.4 -> mode4, opA 0101 -> _1
+Instr16 Assembler::thumb16_mode4_1(ThumbMode4_1Opcode16 opB) {
+  return (B14 | B12 | opB*B9);
+}
+
+
+// A.6.2.4 -> mode4, opA 0110 -> _2
+Instr16 Assembler::thumb16_mode4_2(ThumbMode4_2Opcode16 opB) {
+  return (B14 | B13 | opB*B9);
+}
+
+
+// A.6.2.4 -> mode4, opA 0111 -> _3
+Instr16 Assembler::thumb16_mode4_3(ThumbMode4_3Opcode16 opB) {
+  return (B14 | B13 | B12 | opB*B9);
+}
+
+
+// A.6.2.4 -> mode4, opA 1000 -> _4
+Instr16 Assembler::thumb16_mode4_4(ThumbMode4_4Opcode16 opB) {
+  return (B15 | opB*B9);
+}
+
+
+// A.6.2.4 -> mode4, opA 1001 -> _5
+Instr16 Assembler::thumb16_mode4_5(ThumbMode4_5Opcode16 opB) {
+  return (B15 | B12 | opB*B9);
+}
+
+
+// two low reg r0-r7
+Instr16 Assembler::thumb16_2lowreg_encoding(Register rd,
+                                            const Operand& x) {
+  return (x.rm_.code()*B3 | rd.code());
+}
+
+
+// two low reg r0-r7
+Instr16 Assembler::thumb16_2lowreg_encoding(Register rd,
+                                            Register rs) {
+  return (rs.code()*B3 | rd.code());
+}
+
+
+// imm3 with two low reg
+Instr16 Assembler::thumb16_2lowreg_imm3_encoding(Register rd,
+                                                 Register rn,
+                                                 const Operand& x) {
+  ASSERT(!x.rm_.is_valid());  // is Immediate.
+  ASSERT(is_uint3(x.imm32_));
+  uint16_t imm3 = x.imm32_ & 7;
+  return (imm3*B6 | rn.code()*B3 | rd.code());
+}
+
+
+// imm5 with two low reg
+Instr16 Assembler::thumb16_2lowreg_imm5_encoding(Register rd,
+                                                 Register rn,
+                                                 uint32_t offset) {
+  ASSERT(is_uint5(offset));
+  uint16_t imm5 = offset & 0x1f;
+  return (imm5*B6 | rn.code()*B3 | rd.code());
+}
+
+
+Instr16 Assembler::thumb16_2lowreg_imm5_encoding(Register rd,
+                                                 Register rn,
+                                                 const Operand& x) {
+  ASSERT(!x.rs_.is_valid());
+  ASSERT(is_uint5(x.shift_imm_));
+  uint16_t imm5 = x.shift_imm_ & 0x1f;
+  return (imm5*B6 | rn.code()*B3 | rd.code());
+}
+
+
+// three low reg
+Instr16 Assembler::thumb16_3lowreg_encoding(Register rd,
+                                            const MemOperand& x) {
+  ASSERT(x.rm_.is_valid());  // is Register.
+  return (x.rm_.code()*B6 | x.rn_.code()*B3 | rd.code());
+}
+
+
+Instr16 Assembler::thumb16_3lowreg_encoding(Register rd,
+                                            Register rn,
+                                            const Operand& x) {
+  ASSERT(x.rm_.is_valid());  // is Register.
+  return (x.rm_.code()*B6 | rn.code()*B3 | rd.code());
+}
+
+
+// one any reg
+Instr16 Assembler::thumb16_anyreg_encoding(const Operand& x) {
+  return (x.rm_.code()*B3);
+}
+
+
+// one any reg
+Instr16 Assembler::thumb16_anyreg_encoding(const Register rm) {
+  return (rm.code()*B3);
+}
+
+
+// two any reg
+Instr16 Assembler::thumb16_2anyreg_encoding(Register rd, const Operand& x) {
+  uint16_t d = rd.code() >> 3;
+  return (d*B7 | x.rm_.code()*B3 | (rd.code() & 7));
+}
+
+
+// low reg with imm8
+Instr16 Assembler::thumb16_lowreg_imm8_encoding(Register rd, uint32_t offset) {
+  ASSERT(is_uint8(offset));
+  uint16_t imm8 = offset & 0xff;
+  return (rd.code()*B8 | imm8);
+}
+
+
+Instr16 Assembler::thumb16_lowreg_imm8_encoding(Register rd, const Operand& x) {
+  ASSERT(!x.rm_.is_valid());  // Immediate.
+  ASSERT(is_uint8(x.imm32_));
+  uint16_t imm8 = x.imm32_ & 0xff;
+  return (rd.code()*B8 | imm8);
+}
+
+
+bool Assembler::is_low_reg(Register reg) {
+  return is_uint3(reg.code());
+}
+
+
+bool Assembler::are_low_reg(Register reg1, Register reg2) {
+  return is_uint3(reg1.code()) && is_uint3(reg2.code());
+}
+
+
+Instr16 Assembler::thumb16_instr_at(Address addr) {
+  return Memory::int16_at(addr);
+}
+
+
+void Assembler::thumb16_instr_at_put(int pos, Instr16 instr) {
+  *reinterpret_cast<Instr16*>(buffer_ + pos) = instr;
+}
+
+} }  // namespace v8::internal
+
+#endif  // V8_TARGET_ARCH_ARM
+