Subzero, MIPS32: Intrinsic call Ctlz for i32

src/IceAssemblerMIPS32.cpp

Index: src/IceAssemblerMIPS32.cpp
diff --git a/src/IceAssemblerMIPS32.cpp b/src/IceAssemblerMIPS32.cpp
index 6e8731c70873211e7c133d25b5aeb9e6ce27d2b8..c0a31ee383280048119857cd73595624fed542a7 100644
--- a/src/IceAssemblerMIPS32.cpp
+++ b/src/IceAssemblerMIPS32.cpp
@@ -469,6 +469,16 @@ void AssemblerMIPS32::c_un_s(const Operand *OpFs, const Operand *OpFt) {
                "c.un.s");
 }
 
+void AssemblerMIPS32::clz(const Operand *OpRd, const Operand *OpRs) {
+  IValueT Opcode = 0x70000020;
+  const IValueT Rd = encodeGPRegister(OpRd, "Rd", "clz");
+  const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz");
+  Opcode |= Rd << 11;
+  Opcode |= Rd << 16;
+  Opcode |= Rs << 21;
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::cvt_d_l(const Operand *OpFd, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000021;
   emitCOP1FmtFsFd(Opcode, Long, OpFd, OpFs, "cvt.d.l");
@@ -612,6 +622,12 @@ void AssemblerMIPS32::movf(const Operand *OpRd, const Operand *OpRs,
   emitInst(Opcode);
 }
 
+void AssemblerMIPS32::movn(const Operand *OpRd, const Operand *OpRs,
+                           const Operand *OpRt) {
+  static constexpr IValueT Opcode = 0x44000013;
+  emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movn");
+}
+
 void AssemblerMIPS32::movn_d(const Operand *OpFd, const Operand *OpFs,
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000013;