Subzero, MIPS32: Intrinsic call Ctlz for i32

src/IceAssemblerMIPS32.cpp

 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 451 matching lines @@
   emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
                "c.un.d");
 }
 
 void AssemblerMIPS32::c_un_s(const Operand *OpFs, const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000031;
   emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
                "c.un.s");
 }
 
+void AssemblerMIPS32::clz(const Operand *OpRd, const Operand *OpRs) {
+  IValueT Opcode = 0x70000020;
+  const IValueT Rd = encodeGPRegister(OpRd, "Rd", "clz");
+  const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz");
+  Opcode |= Rd << 11;
+  Opcode |= Rd << 16;
+  Opcode |= Rs << 21;
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::cvt_d_l(const Operand *OpFd, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000021;
   emitCOP1FmtFsFd(Opcode, Long, OpFd, OpFs, "cvt.d.l");
 }
 
 void AssemblerMIPS32::cvt_d_s(const Operand *OpFd, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000021;
   emitCOP1FmtFsFd(Opcode, SinglePrecision, OpFd, OpFs, "cvt.d.s");
 }
 
@@ skipping 123 matching lines @@
     Cc = OpFCC->getFCC();
   }
   const IValueT InstEncodingFalse = 0;
   Opcode |= Rd << 11;
   Opcode |= InstEncodingFalse << 16;
   Opcode |= Cc << 18;
   Opcode |= Rs << 21;
   emitInst(Opcode);
 }
 
+void AssemblerMIPS32::movn(const Operand *OpRd, const Operand *OpRs,
+                           const Operand *OpRt) {
+  static constexpr IValueT Opcode = 0x44000013;
+  emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movn");
+}
+
 void AssemblerMIPS32::movn_d(const Operand *OpFd, const Operand *OpFs,
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000013;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.d");
 }
 
 void AssemblerMIPS32::movn_s(const Operand *OpFd, const Operand *OpFs,
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000013;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s");
@@ skipping 272 matching lines @@
     emitBr(Cond, OpRs, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice