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Side by Side Diff: runtime/vm/assembler_mips.h

Issue 23537030: Better handling of zero in compare and branch for MIPS. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 3 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_ASSEMBLER_MIPS_H_ 5 #ifndef VM_ASSEMBLER_MIPS_H_
6 #define VM_ASSEMBLER_MIPS_H_ 6 #define VM_ASSEMBLER_MIPS_H_
7 7
8 #ifndef VM_ASSEMBLER_H_ 8 #ifndef VM_ASSEMBLER_H_
9 #error Do not include assembler_mips.h directly; use assembler.h instead. 9 #error Do not include assembler_mips.h directly; use assembler.h instead.
10 #endif 10 #endif
(...skipping 841 matching lines...) Expand 10 before | Expand all | Expand 10 after
852 LoadImmediate(TMP1, value); 852 LoadImmediate(TMP1, value);
853 addu(rd, rs, TMP1); 853 addu(rd, rs, TMP1);
854 } 854 }
855 } 855 }
856 856
857 void AddImmediate(Register rd, int32_t value) { 857 void AddImmediate(Register rd, int32_t value) {
858 AddImmediate(rd, rd, value); 858 AddImmediate(rd, rd, value);
859 } 859 }
860 860
861 void BranchEqual(Register rd, int32_t value, Label* l) { 861 void BranchEqual(Register rd, int32_t value, Label* l) {
862 ASSERT(rd != CMPRES2); 862 if (value == 0) {
863 LoadImmediate(CMPRES2, value); 863 beq(rd, ZR, l);
864 beq(rd, CMPRES2, l); 864 } else {
865 ASSERT(rd != CMPRES2);
866 LoadImmediate(CMPRES2, value);
867 beq(rd, CMPRES2, l);
868 }
865 } 869 }
866 870
867 void BranchEqual(Register rd, const Object& object, Label* l) { 871 void BranchEqual(Register rd, const Object& object, Label* l) {
868 ASSERT(rd != CMPRES2); 872 ASSERT(rd != CMPRES2);
869 LoadObject(CMPRES2, object); 873 LoadObject(CMPRES2, object);
870 beq(rd, CMPRES2, l); 874 beq(rd, CMPRES2, l);
871 } 875 }
872 876
873 void BranchNotEqual(Register rd, int32_t value, Label* l) { 877 void BranchNotEqual(Register rd, int32_t value, Label* l) {
874 ASSERT(rd != CMPRES2); 878 if (value == 0) {
875 LoadImmediate(CMPRES2, value); 879 bne(rd, ZR, l);
876 bne(rd, CMPRES2, l); 880 } else {
881 ASSERT(rd != CMPRES2);
882 LoadImmediate(CMPRES2, value);
883 bne(rd, CMPRES2, l);
884 }
877 } 885 }
878 886
879 void BranchNotEqual(Register rd, const Object& object, Label* l) { 887 void BranchNotEqual(Register rd, const Object& object, Label* l) {
880 ASSERT(rd != CMPRES2); 888 ASSERT(rd != CMPRES2);
881 LoadObject(CMPRES2, object); 889 LoadObject(CMPRES2, object);
882 bne(rd, CMPRES2, l); 890 bne(rd, CMPRES2, l);
883 } 891 }
884 892
885 void BranchSignedGreater(Register rd, Register rs, Label* l) { 893 void BranchSignedGreater(Register rd, Register rs, Label* l) {
886 slt(CMPRES2, rs, rd); // CMPRES2 = rd > rs ? 1 : 0. 894 slt(CMPRES2, rs, rd); // CMPRES2 = rd > rs ? 1 : 0.
887 bne(CMPRES2, ZR, l); 895 bne(CMPRES2, ZR, l);
888 } 896 }
889 897
890 void BranchSignedGreater(Register rd, int32_t value, Label* l) { 898 void BranchSignedGreater(Register rd, int32_t value, Label* l) {
891 ASSERT(rd != CMPRES2); 899 if (value == 0) {
892 LoadImmediate(CMPRES2, value); 900 bgtz(rd, l);
893 BranchSignedGreater(rd, CMPRES2, l); 901 } else {
902 ASSERT(rd != CMPRES2);
903 LoadImmediate(CMPRES2, value);
904 BranchSignedGreater(rd, CMPRES2, l);
905 }
894 } 906 }
895 907
896 void BranchUnsignedGreater(Register rd, Register rs, Label* l) { 908 void BranchUnsignedGreater(Register rd, Register rs, Label* l) {
897 sltu(CMPRES2, rs, rd); 909 sltu(CMPRES2, rs, rd);
898 bne(CMPRES2, ZR, l); 910 bne(CMPRES2, ZR, l);
899 } 911 }
900 912
901 void BranchUnsignedGreater(Register rd, int32_t value, Label* l) { 913 void BranchUnsignedGreater(Register rd, int32_t value, Label* l) {
902 ASSERT(rd != CMPRES2); 914 if (value == 0) {
903 LoadImmediate(CMPRES2, value); 915 BranchNotEqual(rd, 0, l);
904 BranchUnsignedGreater(rd, CMPRES2, l); 916 } else {
917 ASSERT(rd != CMPRES2);
918 LoadImmediate(CMPRES2, value);
919 BranchUnsignedGreater(rd, CMPRES2, l);
920 }
905 } 921 }
906 922
907 void BranchSignedGreaterEqual(Register rd, Register rs, Label* l) { 923 void BranchSignedGreaterEqual(Register rd, Register rs, Label* l) {
908 slt(CMPRES2, rd, rs); // CMPRES2 = rd < rs ? 1 : 0. 924 slt(CMPRES2, rd, rs); // CMPRES2 = rd < rs ? 1 : 0.
909 beq(CMPRES2, ZR, l); // If CMPRES2 = 0, then rd >= rs. 925 beq(CMPRES2, ZR, l); // If CMPRES2 = 0, then rd >= rs.
910 } 926 }
911 927
912 void BranchSignedGreaterEqual(Register rd, int32_t value, Label* l) { 928 void BranchSignedGreaterEqual(Register rd, int32_t value, Label* l) {
913 if (Utils::IsInt(kImmBits, value)) { 929 if (value == 0) {
914 slti(CMPRES2, rd, Immediate(value)); 930 bgez(rd, l);
915 beq(CMPRES2, ZR, l);
916 } else { 931 } else {
917 ASSERT(rd != CMPRES2); 932 if (Utils::IsInt(kImmBits, value)) {
918 LoadImmediate(CMPRES2, value); 933 slti(CMPRES2, rd, Immediate(value));
919 BranchSignedGreaterEqual(rd, CMPRES2, l); 934 beq(CMPRES2, ZR, l);
935 } else {
936 ASSERT(rd != CMPRES2);
937 LoadImmediate(CMPRES2, value);
938 BranchSignedGreaterEqual(rd, CMPRES2, l);
939 }
920 } 940 }
921 } 941 }
922 942
923 void BranchUnsignedGreaterEqual(Register rd, Register rs, Label* l) { 943 void BranchUnsignedGreaterEqual(Register rd, Register rs, Label* l) {
924 sltu(CMPRES2, rd, rs); // CMPRES2 = rd < rs ? 1 : 0. 944 sltu(CMPRES2, rd, rs); // CMPRES2 = rd < rs ? 1 : 0.
925 beq(CMPRES2, ZR, l); 945 beq(CMPRES2, ZR, l);
926 } 946 }
927 947
928 void BranchUnsignedGreaterEqual(Register rd, int32_t value, Label* l) { 948 void BranchUnsignedGreaterEqual(Register rd, int32_t value, Label* l) {
929 if (Utils::IsUint(kImmBits, value)) { 949 if (value == 0) {
930 sltiu(CMPRES2, rd, Immediate(value)); 950 b(l);
931 beq(CMPRES2, ZR, l);
932 } else { 951 } else {
933 ASSERT(rd != CMPRES2); 952 if (Utils::IsUint(kImmBits, value)) {
934 LoadImmediate(CMPRES2, value); 953 sltiu(CMPRES2, rd, Immediate(value));
935 BranchUnsignedGreaterEqual(rd, CMPRES2, l); 954 beq(CMPRES2, ZR, l);
955 } else {
956 ASSERT(rd != CMPRES2);
957 LoadImmediate(CMPRES2, value);
958 BranchUnsignedGreaterEqual(rd, CMPRES2, l);
959 }
936 } 960 }
937 } 961 }
938 962
939 void BranchSignedLess(Register rd, Register rs, Label* l) { 963 void BranchSignedLess(Register rd, Register rs, Label* l) {
940 BranchSignedGreater(rs, rd, l); 964 BranchSignedGreater(rs, rd, l);
941 } 965 }
942 966
943 void BranchSignedLess(Register rd, int32_t value, Label* l) { 967 void BranchSignedLess(Register rd, int32_t value, Label* l) {
944 if (Utils::IsInt(kImmBits, value)) { 968 if (value == 0) {
945 slti(CMPRES2, rd, Immediate(value)); 969 bltz(rd, l);
946 bne(CMPRES2, ZR, l);
947 } else { 970 } else {
948 ASSERT(rd != CMPRES2); 971 if (Utils::IsInt(kImmBits, value)) {
949 LoadImmediate(CMPRES2, value); 972 slti(CMPRES2, rd, Immediate(value));
950 BranchSignedGreater(CMPRES2, rd, l); 973 bne(CMPRES2, ZR, l);
974 } else {
975 ASSERT(rd != CMPRES2);
976 LoadImmediate(CMPRES2, value);
977 BranchSignedGreater(CMPRES2, rd, l);
978 }
951 } 979 }
952 } 980 }
953 981
954 void BranchUnsignedLess(Register rd, Register rs, Label* l) { 982 void BranchUnsignedLess(Register rd, Register rs, Label* l) {
955 BranchUnsignedGreater(rs, rd, l); 983 BranchUnsignedGreater(rs, rd, l);
956 } 984 }
957 985
958 void BranchUnsignedLess(Register rd, int32_t value, Label* l) { 986 void BranchUnsignedLess(Register rd, int32_t value, Label* l) {
987 ASSERT(value != 0);
959 if (Utils::IsUint(kImmBits, value)) { 988 if (Utils::IsUint(kImmBits, value)) {
960 sltiu(CMPRES2, rd, Immediate(value)); 989 sltiu(CMPRES2, rd, Immediate(value));
961 bne(CMPRES2, ZR, l); 990 bne(CMPRES2, ZR, l);
962 } else { 991 } else {
963 ASSERT(rd != CMPRES2); 992 ASSERT(rd != CMPRES2);
964 LoadImmediate(CMPRES2, value); 993 LoadImmediate(CMPRES2, value);
965 BranchUnsignedGreater(CMPRES2, rd, l); 994 BranchUnsignedGreater(CMPRES2, rd, l);
966 } 995 }
967 } 996 }
968 997
969 void BranchSignedLessEqual(Register rd, Register rs, Label* l) { 998 void BranchSignedLessEqual(Register rd, Register rs, Label* l) {
970 BranchSignedGreaterEqual(rs, rd, l); 999 BranchSignedGreaterEqual(rs, rd, l);
971 } 1000 }
972 1001
973 void BranchSignedLessEqual(Register rd, int32_t value, Label* l) { 1002 void BranchSignedLessEqual(Register rd, int32_t value, Label* l) {
974 ASSERT(rd != CMPRES2); 1003 if (value == 0) {
975 LoadImmediate(CMPRES2, value); 1004 blez(rd, l);
976 BranchSignedGreaterEqual(CMPRES2, rd, l); 1005 } else {
1006 ASSERT(rd != CMPRES2);
1007 LoadImmediate(CMPRES2, value);
1008 BranchSignedGreaterEqual(CMPRES2, rd, l);
1009 }
977 } 1010 }
978 1011
979 void BranchUnsignedLessEqual(Register rd, Register rs, Label* l) { 1012 void BranchUnsignedLessEqual(Register rd, Register rs, Label* l) {
980 BranchUnsignedGreaterEqual(rs, rd, l); 1013 BranchUnsignedGreaterEqual(rs, rd, l);
981 } 1014 }
982 1015
983 void BranchUnsignedLessEqual(Register rd, int32_t value, Label* l) { 1016 void BranchUnsignedLessEqual(Register rd, int32_t value, Label* l) {
984 ASSERT(rd != CMPRES2); 1017 ASSERT(rd != CMPRES2);
985 LoadImmediate(CMPRES2, value); 1018 LoadImmediate(CMPRES2, value);
986 BranchUnsignedGreaterEqual(CMPRES2, rd, l); 1019 BranchUnsignedGreaterEqual(CMPRES2, rd, l);
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1222 Register value, 1255 Register value,
1223 Label* no_update); 1256 Label* no_update);
1224 1257
1225 DISALLOW_ALLOCATION(); 1258 DISALLOW_ALLOCATION();
1226 DISALLOW_COPY_AND_ASSIGN(Assembler); 1259 DISALLOW_COPY_AND_ASSIGN(Assembler);
1227 }; 1260 };
1228 1261
1229 } // namespace dart 1262 } // namespace dart
1230 1263
1231 #endif // VM_ASSEMBLER_MIPS_H_ 1264 #endif // VM_ASSEMBLER_MIPS_H_
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