Adds comparisons, labels, branches to arm64

runtime/vm/disassembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 #include "platform/assert.h"
 
@@ skipping 16 matching lines @@
 
  private:
   // Bottleneck functions to print into the out_buffer.
   void Print(const char* str);
 
   // Printing of common values.
   void PrintRegister(int reg, R31Type r31t);
   void PrintShiftExtendRm(Instr* instr);
   void PrintMemOperand(Instr* instr);
   void PrintS(Instr* instr);
+  void PrintCondition(Instr* instr);
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instr* instr, const char* option);
   int FormatOption(Instr* instr, const char* format);
   void Format(Instr* instr, const char* format);
   void Unknown(Instr* instr);
 
   // Decode instructions.
   #define DECODE_OP(op)                                                        \
     void Decode##op(Instr* instr);
@@ skipping 61 matching lines @@
   "lsl", "lsr", "asr", "ror"
 };
 
 
 static const char* extend_names[kMaxExtend] = {
   "uxtb", "uxth", "uxtw", "uxtx",
   "sxtb", "sxth", "sxtw", "sxtx",
 };
 
 
+// These condition names are defined in a way to match the native disassembler
+// formatting. See for example the command "objdump -d <binary file>".
+static const char* cond_names[kMaxCondition] = {
+  "eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" ,
+  "hi", "ls", "ge", "lt", "gt", "le", "", "invalid",
+};
+
+
+// Print the condition guarding the instruction.
+void ARM64Decoder::PrintCondition(Instr* instr) {
+  Print(cond_names[instr->ConditionField()]);
+}
+
+
 // Print the register shift operands for the instruction. Generally used for
 // data processing instructions.
 void ARM64Decoder::PrintShiftExtendRm(Instr* instr) {
   int rm = instr->RmField();
   Shift shift = instr->ShiftTypeField();
   int shift_amount = instr->ShiftAmountField();
   Extend extend = instr->ExtendTypeField();
   int extend_shift_amount = instr->ExtShiftAmountField();
 
   PrintRegister(rm, R31IsZR);
@@ skipping 128 matching lines @@
 }
 
 
 // FormatOption takes a formatting string and interprets it based on
 // the current instructions. The format string points to the first
 // character of the option string (the option escape has already been
 // consumed by the caller.)  FormatOption returns the number of
 // characters that were consumed from the formatting string.
 int ARM64Decoder::FormatOption(Instr* instr, const char* format) {
   switch (format[0]) {
+    case 'b': {
+      if (format[3] == 'i') {
+        ASSERT(STRING_STARTS_WITH(format, "bitimm"));
+        const uint64_t imm = instr->ImmLogical();
+        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                   remaining_size_in_buffer(),
+                                   "0x%"Px64,
+                                   imm);
+        return 6;
+      } else {
+        ASSERT(STRING_STARTS_WITH(format, "bitpos"));
+        int bitpos = instr->Bits(19, 4) | (instr->Bit(31) << 5);
+        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                   remaining_size_in_buffer(),
+                                   "#%d",
+                                   bitpos);
+        return 6;
+      }
+    }
+    case 'c': {
+      ASSERT(STRING_STARTS_WITH(format, "cond"));
+      PrintCondition(instr);
+      return 4;
+    }
+    case 'd': {
+      if (format[4] == '2') {
+        ASSERT(STRING_STARTS_WITH(format, "dest26"));
+        int64_t off = instr->SImm26Field() << 2;
+        uword destination = reinterpret_cast<uword>(instr) + off;
+        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                   remaining_size_in_buffer(),
+                                   "%#" Px "",
+                                   destination);
+      } else {
+        if (format[5] == '4') {
+          ASSERT(STRING_STARTS_WITH(format, "dest14"));
+          int64_t off = instr->SImm14Field() << 2;
+          uword destination = reinterpret_cast<uword>(instr) + off;
+          buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                     remaining_size_in_buffer(),
+                                     "%#" Px "",
+                                     destination);
+        } else {
+          ASSERT(STRING_STARTS_WITH(format, "dest19"));
+          int64_t off = instr->SImm19Field() << 2;
+          uword destination = reinterpret_cast<uword>(instr) + off;
+          buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                     remaining_size_in_buffer(),
+                                     "%#" Px "",
+                                     destination);
+        }
+      }
+      return 6;
+    }
+    case 'h': {
+      ASSERT(STRING_STARTS_WITH(format, "hw"));
+      const int shift = instr->HWField() << 4;
+      if (shift != 0) {
+        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                   remaining_size_in_buffer(),
+                                   "lsl %d",
+                                   shift);
+      }
+      return 2;
+    }
     case 'i': {  // 'imm12, imm16
       uint64_t imm;
       int ret = 5;
       if (format[4] == '2') {
         ASSERT(STRING_STARTS_WITH(format, "imm12"));
         imm = instr->Imm12Field();
         if (format[5] == 's') {
           // shifted immediate.
           if (instr->Imm12ShiftField() == 1) {
             imm = imm << 12;
           } else if ((instr->Imm12ShiftField() & 0x2) != 0) {
             Print("Unknown Shift");
           }
           ret = 6;
         }
       } else {
         ASSERT(STRING_STARTS_WITH(format, "imm16"));
         imm = instr->Imm16Field();
       }
       buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
                                  remaining_size_in_buffer(),
                                  "0x%"Px64,
                                  imm);
       return ret;
     }
+    case 'm': {
+      ASSERT(STRING_STARTS_WITH(format, "memop"));
+      PrintMemOperand(instr);
+      return 5;
+    }
+    case 'p': {
+      ASSERT(STRING_STARTS_WITH(format, "pcrel"));
+      const int64_t immhi = instr->SImm19Field();
+      const int64_t immlo = instr->Bits(29, 2);
+      const int64_t off = (immhi << 2) | immlo;
+      const int64_t pc = reinterpret_cast<int64_t>(instr);
+      const int64_t dest = pc + off;
+      buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                 remaining_size_in_buffer(),
+                                 "0x%"Px64,
+                                 dest);
+      return 5;
+    }
+    case 'r': {
+      return FormatRegister(instr, format);
+    }
     case 's': {  // 's: S flag.
       if (format[1] == 'h') {
         ASSERT(STRING_STARTS_WITH(format, "shift_op"));
         PrintShiftExtendRm(instr);
         return 8;
       } else if (format[1] == 'f') {
         ASSERT(STRING_STARTS_WITH(format, "sf"));
         if (instr->SFField() == 1) {
           // TODO(zra): If we don't use the w form much, we can omit printing
           // this x.
@@ skipping 20 matching lines @@
         return 2;
       } else if (format[1] == ' ') {
         if (instr->HasS()) {
           Print("s");
         }
         return 1;
       } else {
         UNREACHABLE();
       }
     }
-    case 'r': {
-      return FormatRegister(instr, format);
-    }
-    case 'h': {
-      ASSERT(STRING_STARTS_WITH(format, "hw"));
-      const int shift = instr->HWField() << 4;
-      if (shift != 0) {
-        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                   remaining_size_in_buffer(),
-                                   "lsl %d",
-                                   shift);
-      }
-      return 2;
-    }
-    case 'm': {
-      ASSERT(STRING_STARTS_WITH(format, "memop"));
-      PrintMemOperand(instr);
-      return 5;
-    }
-    case 'b': {
-      ASSERT(STRING_STARTS_WITH(format, "bitimm"));
-      const uint64_t imm = instr->ImmLogical();
-      buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
-                                 remaining_size_in_buffer(),
-                                 "0x%"Px64,
-                                 imm);
-      return 6;
-    }
     default: {
       UNREACHABLE();
       break;
     }
   }
   UNREACHABLE();
   return -1;
 }
 
 
@@ skipping 92 matching lines @@
     case 3:
       Format(instr, "andi'sfs 'rd, 'rn, 'bitimm");
       break;
     default:
       Unknown(instr);
       break;
   }
 }
 
 
+void ARM64Decoder::DecodePCRel(Instr* instr) {
+  const int op = instr->Bit(31);
+  if (op == 0) {
+    Format(instr, "adr 'rd, 'pcrel");
+  } else {
+    Unknown(instr);
+  }
+}
+
+
 void ARM64Decoder::DecodeDPImmediate(Instr* instr) {
   if (instr->IsMoveWideOp()) {
     DecodeMoveWide(instr);
   } else if (instr->IsAddSubImmOp()) {
     DecodeAddSubImm(instr);
   } else if (instr->IsLogicalImmOp()) {
     DecodeLogicalImm(instr);
+  } else if (instr->IsPCRelOp()) {
+    DecodePCRel(instr);
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeExceptionGen(Instr* instr) {
   if ((instr->Bits(0, 2) == 1) && (instr->Bits(2, 3) == 0) &&
       (instr->Bits(21, 3) == 0)) {
     Format(instr, "svc 'imm16");
@@ skipping 36 matching lines @@
         Format(instr, "ret 'rn");
         break;
       default:
         Unknown(instr);
         break;
     }
   }
 }
 
 
+void ARM64Decoder::DecodeCompareAndBranch(Instr* instr) {
+  const int op = instr->Bit(24);
+  if (op == 0) {
+    Format(instr, "cbz'sf 'rt, 'dest19");
+  } else {
+    Format(instr, "cbnz'sf 'rt, 'dest19");
+  }
+}
+
+
+void ARM64Decoder::DecodeConditionalBranch(Instr* instr) {
+  if ((instr->Bit(24) != 0) || (instr->Bit(4) != 0)) {
+    Unknown(instr);
+    return;
+  }
+  Format(instr, "b'cond 'dest19");
+}
+
+
+void ARM64Decoder::DecodeTestAndBranch(Instr* instr) {
+  const int op = instr->Bit(24);
+  if (op == 0) {
+    Format(instr, "tbz'sf 'rt, 'bitpos, 'dest14");
+  } else {
+    Format(instr, "tbnz'sf 'rt, 'bitpos, 'dest14");
+  }
+}
+
+
+void ARM64Decoder::DecodeUnconditionalBranch(Instr* instr) {
+  const int op = instr->Bit(31);
+  if (op == 0) {
+    Format(instr, "b 'dest26");
+  } else {
+    Format(instr, "bl 'dest26");
+  }
+}
+
 void ARM64Decoder::DecodeCompareBranch(Instr* instr) {
   if (instr->IsExceptionGenOp()) {
     DecodeExceptionGen(instr);
   } else if (instr->IsSystemOp()) {
     DecodeSystem(instr);
   } else if (instr->IsUnconditionalBranchRegOp()) {
     DecodeUnconditionalBranchReg(instr);
+  } else if (instr->IsCompareAndBranchOp()) {
+    DecodeCompareAndBranch(instr);
+  } else if (instr->IsConditionalBranchOp()) {
+    DecodeConditionalBranch(instr);
+  } else if (instr->IsTestAndBranchOp()) {
+    DecodeTestAndBranch(instr);
+  } else if (instr->IsUnconditionalBranchOp()) {
+    DecodeUnconditionalBranch(instr);
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeLoadStore(Instr* instr) {
   if (instr->IsLoadStoreRegOp()) {
     DecodeLoadStoreReg(instr);
   } else {
@@ skipping 143 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM