Adds comparisons, labels, branches to arm64

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM64_H_
 #define VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 241 matching lines @@
   DPRegisterMask = 0x0e000000,
   DPRegisterFixed = B27 | B25,
 
   DPSimd1Mask = 0x1e000000,
   DPSimd1Fixed = B27 | B26 | B25,
 
   DPSimd2Mask = 0x1e000000,
   DPSimd2Fixed = B28 | DPSimd1Fixed,
 };
 
+// C3.2.1
+enum CompareAndBranchOp {
+  CompareAndBranchMask = 0x7e000000,
+  CompareAndBranchFixed = CompareBranchFixed | B29,
+  CBZ = CompareBranchFixed,
+  CBNZ = CompareBranchFixed | B24,
+};
+
+// C.3.2.2
+enum ConditionalBranchOp {
+  ConditionalBranchMask = 0xfe000000,
+  ConditionalBranchFixed = CompareBranchFixed | B30,
+  BCOND = ConditionalBranchFixed,
+};
+
 // C3.2.3
 enum ExceptionGenOp {
   ExceptionGenMask = 0xff000000,
   ExceptionGenFixed = CompareBranchFixed | B31 | B30,
   SVC = ExceptionGenFixed | B0,
   BRK = ExceptionGenFixed | B21,
   HLT = ExceptionGenFixed | B22,
 };
 
 // C3.2.4
 enum SystemOp {
   SystemMask = 0xffc00000,
   SystemFixed = CompareBranchFixed | B31 | B30 | B24,
   HINT = SystemFixed | B17 | B16 | B13 | B4 | B3 | B2 | B1 | B0,
 };
 
+// C3.2.5
+enum TestAndBranchOp {
+  TestAndBranchMask = 0x7e000000,
+  TestAndBranchFixed = CompareBranchFixed | B29 | B25,
+  TBZ = TestAndBranchFixed,
+  TBNZ = TestAndBranchFixed | B24,
+};
+
+// C3.2.6
+enum UnconditionalBranchOp {
+  UnconditionalBranchMask = 0x7c000000,
+  UnconditionalBranchFixed = CompareBranchFixed,
+  B = UnconditionalBranchFixed,
+  BL = UnconditionalBranchFixed | B31,
+};
+
 // C3.2.7
 enum UnconditionalBranchRegOp {
   UnconditionalBranchRegMask = 0xfe000000,
   UnconditionalBranchRegFixed = CompareBranchFixed | B31 | B30 | B25,
   BR = UnconditionalBranchRegFixed | B20 | B19 | B18 | B17 | B16,
   BLR = BR | B21,
   RET = BR | B22,
 };
 
 enum LoadStoreRegOp {
@@ skipping 23 matching lines @@
 
 // C3.4.5
 enum MoveWideOp {
   MoveWideMask = 0x1f800000,
   MoveWideFixed = DPImmediateFixed | B25 | B23,
   MOVN = MoveWideFixed,
   MOVZ = MoveWideFixed | B30,
   MOVK = MoveWideFixed | B30 | B29,
 };
 
+// C3.4.6
+enum PCRelOp {
+  PCRelMask = 0x1f000000,
+  PCRelFixed = DPImmediateFixed,
+  ADR = PCRelFixed,
+  ADRP = PCRelFixed | B31,
+};
+
 // C3.5.1
 enum AddSubShiftExtOp {
   AddSubShiftExtMask = 0x1f000000,
   AddSubShiftExtFixed = DPRegisterFixed | B24,
   ADD = AddSubShiftExtFixed,
   SUB = AddSubShiftExtFixed | B30,
 };
 
 enum LogicalShiftOp {
   LogicalShiftMask = 0x1f000000,
   LogicalShiftFixed = DPRegisterFixed,
   AND = LogicalShiftFixed,
   BIC = LogicalShiftFixed | B21,
   ORR = LogicalShiftFixed | B29,
   ORN = LogicalShiftFixed | B29 | B21,
   EOR = LogicalShiftFixed | B30,
   EON = LogicalShiftFixed | B30 | B21,
   ANDS = LogicalShiftFixed | B30 | B29,
   BICS = LogicalShiftFixed | B30 | B29 | B21,
 };
 
 #define APPLY_OP_LIST(_V)                                                      \
 _V(DPImmediate)                                                                \
 _V(CompareBranch)                                                              \
 _V(LoadStore)                                                                  \
 _V(DPRegister)                                                                 \
 _V(DPSimd1)                                                                    \
 _V(DPSimd2)                                                                    \
+_V(CompareAndBranch)                                                           \
+_V(ConditionalBranch)                                                          \
 _V(ExceptionGen)                                                               \
 _V(System)                                                                     \
+_V(TestAndBranch)                                                              \
+_V(UnconditionalBranch)                                                        \
+_V(UnconditionalBranchReg)                                                     \
 _V(LoadStoreReg)                                                               \
-_V(UnconditionalBranchReg)                                                     \
 _V(AddSubImm)                                                                  \
 _V(LogicalImm)                                                                 \
 _V(MoveWide)                                                                   \
+_V(PCRel)                                                                      \
 _V(AddSubShiftExt)                                                             \
 _V(LogicalShift)                                                               \
 
 
 enum Shift {
   kNoShift = -1,
   LSL = 0,  // Logical shift left
   LSR = 1,  // Logical shift right
   ASR = 2,  // Arithmetic shift right
   ROR = 3,  // Rotate right
@@ skipping 50 matching lines @@
   kImm3Shift = 10,
   kImm3Bits = 3,
   kImm6Shift = 10,
   kImm6Bits = 6,
   kImm9Shift = 12,
   kImm9Bits = 9,
   kImm12Shift = 10,
   kImm12Bits = 12,
   kImm12ShiftShift = 22,
   kImm12ShiftBits = 2,
+  kImm14Shift = 5,
+  kImm14Bits = 14,
   kImm16Shift = 5,
   kImm16Bits = 16,
+  kImm19Shift = 5,
+  kImm19Bits = 19,
+  kImm19Mask = 0x7ffff,
+  kImm26Shift = 0,
+  kImm26Bits = 26,
+
+  kCondShift = 0,
+  kCondBits = 4,
 
   // Bitfield immediates.
   kNShift = 22,
   kNBits = 1,
   kImmRShift = 16,
   kImmRBits = 6,
   kImmSShift = 10,
   kImmSBits = 6,
 
   kHWShift = 21,
@@ skipping 112 matching lines @@
   inline int Imm12Field() const { return Bits(kImm12Shift, kImm12Bits); }
   inline int Imm12ShiftField() const {
     return Bits(kImm12ShiftShift, kImm12ShiftBits); }
 
   inline int Imm16Field() const { return Bits(kImm16Shift, kImm16Bits); }
   inline int HWField() const { return Bits(kHWShift, kHWBits); }
 
   inline int ImmRField() const { return Bits(kImmRShift, kImmRBits); }
   inline int ImmSField() const { return Bits(kImmSShift, kImmSBits); }
 
+  inline int Imm14Field() const { return Bits(kImm14Shift, kImm14Bits); }
+  inline int64_t SImm14Field() const {
+      return (static_cast<int32_t>(Imm14Field()) << 18) >> 18; }
+  inline int Imm19Field() const { return Bits(kImm19Shift, kImm19Bits); }
+  inline int64_t SImm19Field() const {
+      return (static_cast<int32_t>(Imm19Field()) << 13) >> 13; }
+  inline int Imm26Field() const { return Bits(kImm26Shift, kImm26Bits); }
+  inline int64_t SImm26Field() const {
+      return (static_cast<int32_t>(Imm26Field()) << 6) >> 6; }
+
+  inline Condition ConditionField() const {
+    return static_cast<Condition>(Bits(kCondShift, kCondBits));
+  }
+
   // Shift and Extend.
   inline bool IsShift() const {
     return IsLogicalShiftOp() || (Bit(kAddShiftExtendShift) == 0);
   }
   inline bool IsExtend() const {
     return !IsLogicalShiftOp() && (Bit(kAddShiftExtendShift) == 1);
   }
   inline Shift ShiftTypeField() const {
       return static_cast<Shift>(Bits(kShiftTypeShift, kShiftTypeBits)); }
   inline Extend ExtendTypeField() const {
@@ skipping 105 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM64_H_