Adds comparisons, labels, branches to arm64

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 260 matching lines @@
   ~Assembler() { }
 
   void PopRegister(Register r) {
     UNIMPLEMENTED();
   }
 
   void Drop(intptr_t stack_elements) {
     UNIMPLEMENTED();
   }
 
-  void Bind(Label* label) {
-    UNIMPLEMENTED();
-  }
+  void Bind(Label* label);
 
   // Misc. functionality
   intptr_t CodeSize() const { return buffer_.Size(); }
   intptr_t prologue_offset() const { return prologue_offset_; }
 
   // Count the fixups that produce a pointer offset, without processing
   // the fixups.  On ARM64 there are no pointers in code.
   intptr_t CountPointerOffsets() const { return 0; }
 
   const ZoneGrowableArray<intptr_t>& GetPointerOffsets() const {
@@ skipping 55 matching lines @@
   void addw(Register rd, Register rn, Operand o) {
     AddSubHelper(kWord, false, false, rd, rn, o);
   }
   void sub(Register rd, Register rn, Operand o) {
     AddSubHelper(kDoubleWord, false, true, rd, rn, o);
   }
   void subs(Register rd, Register rn, Operand o) {
     AddSubHelper(kDoubleWord, true, true, rd, rn, o);
   }
 
+  // PC relative immediate add. imm is in bytes.
+  void adr(Register rd, int64_t imm) {
+    EmitPCRelOp(ADR, rd, imm);
+  }
+
   // Logical immediate operations.
   // TODO(zra): Add macros that check IsImmLogical, and fall back on a longer
   // sequence on failure.
   void andi(Register rd, Register rn, uint64_t imm) {
     Operand imm_op;
     const bool immok = IsImmLogical(imm, kXRegSizeInBits, &imm_op);
     ASSERT(immok);
     EmitLogicalImmOp(ANDI, rd, rn, imm_op, kDoubleWord);
   }
   void orri(Register rd, Register rn, uint64_t imm) {
@@ skipping 34 matching lines @@
   void eon(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(EON, rd, rn, o, kDoubleWord);
   }
   void ands(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(ANDS, rd, rn, o, kDoubleWord);
   }
   void bics(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(BICS, rd, rn, o, kDoubleWord);
   }
 
-  // Comparison.
-  // rn cmp o.
-  void cmp(Register rn, Operand o) {
-    subs(ZR, rn, o);
-  }
-  // rn cmp -o.
-  void cmn(Register rn, Operand o) {
-    adds(ZR, rn, o);
-  }
-
   // Move wide immediate.
   void movk(Register rd, int32_t imm, int32_t hw_idx) {
     ASSERT(rd != SP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVK, crd, imm, hw_idx, kDoubleWord);
   }
   void movn(Register rd, int32_t imm, int32_t hw_idx) {
     ASSERT(rd != SP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVN, crd, imm, hw_idx, kDoubleWord);
@@ skipping 11 matching lines @@
     // writeback, which is unlikely to be useful.
     ASSERT(((a.type() != Address::PreIndex) &&
             (a.type() != Address::PostIndex)) ||
            (rt != a.base()));
     EmitLoadStoreReg(LDR, rt, a, kDoubleWord);
   }
   void str(Register rt, Address a) {
     EmitLoadStoreReg(STR, rt, a, kDoubleWord);
   }
 
-  // Function return.
+  // Comparison.
+  // rn cmp o.
+  void cmp(Register rn, Operand o) {
+    subs(ZR, rn, o);
+  }
+  // rn cmp -o.
+  void cmn(Register rn, Operand o) {
+    adds(ZR, rn, o);
+  }
+
+  // Conditional branch.
+  void b(Label* label, Condition cond = AL) {
+    EmitBranch(BCOND, cond, label);
+  }
+
+  // TODO(zra): branch and link with imm26 offset.
+  // TODO(zra): cbz, cbnz.
+
+  // Branch, link, return.
+  void br(Register rn) {
+    EmitUnconditionalBranchRegOp(BR, rn);
+  }
+  void blr(Register rn) {
+    EmitUnconditionalBranchRegOp(BLR, rn);
+  }
   void ret(Register rn = R30) {
     EmitUnconditionalBranchRegOp(RET, rn);
   }
 
  private:
   AssemblerBuffer buffer_;  // Contains position independent code.
   GrowableObjectArray& object_pool_;  // Objects and patchable jump targets.
   int32_t prologue_offset_;
 
   bool use_far_branches_;
@@ skipping 16 matching lines @@
   GrowableArray<CodeComment*> comments_;
 
   bool IsImmLogical(uint64_t value, uint8_t width, Operand* imm_op);
 
   void AddSubHelper(OperandSize os, bool set_flags, bool subtract,
                     Register rd, Register rn, Operand o) {
     ASSERT((rd != R31) && (rn != R31));
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     if (o.type() == Operand::Immediate) {
-      ASSERT((rd != ZR) && (rn != ZR));
+      ASSERT(rn != ZR);
       EmitAddSubImmOp(subtract ? SUBI : ADDI, crd, crn, o, os, set_flags);
     } else if (o.type() == Operand::Shifted) {
       ASSERT((rd != SP) && (rn != SP));
       EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
     } else {
       ASSERT(o.type() == Operand::Extended);
       ASSERT((rd != SP) && (rn != ZR));
       EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
     }
   }
@@ skipping 54 matching lines @@
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t s = set_flags ? B29 : 0;
     const int32_t encoding =
         op | size | s |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(rn) << kRnShift) |
         o.encoding();
     Emit(encoding);
   }
 
+  int32_t EncodeImm19BranchOffset(int64_t imm, int32_t instr) {
+    const int32_t imm32 = static_cast<int32_t>(imm);
+    const int32_t off = (((imm32 >> 2) & kImm19Mask) << kImm19Shift);
+    return (instr & ~(kImm19Mask << kImm19Shift)) | off;
+  }
+
+  int64_t DecodeImm19BranchOffset(int32_t instr) {
+    const int32_t off = (((instr >> kImm19Shift) & kImm19Shift) << 13) >> 13;
+    return static_cast<int64_t>(off);
+  }
+
+  void EmitCompareAndBranch(CompareAndBranchOp op, Register rt, int64_t imm,
+                            OperandSize sz) {
+    ASSERT((sz == kDoubleWord) || (sz == kWord));
+    ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
+    const int32_t size = (sz == kDoubleWord) ? B31 : 0;
+    const int32_t encoded_offset = EncodeImm19BranchOffset(imm, 0);
+    const int32_t encoding =
+        op | size |
+        (static_cast<int32_t>(rt) << kRtShift) |
+        encoded_offset;
+    Emit(encoding);
+  }
+
+  void EmitConditionalBranch(ConditionalBranchOp op, Condition cond,
+                             int64_t imm) {
+    ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
+    const int32_t encoding =
+        op |
+        (static_cast<int32_t>(cond) << kCondShift) |
+        (((imm >> 2) & kImm19Mask) << kImm19Shift);
+    Emit(encoding);
+  }
+
+  bool CanEncodeImm19BranchOffset(int64_t offset) {
+    ASSERT(Utils::IsAligned(offset, 4));
+    return Utils::IsInt(19, offset);
+  }
+
+  // TODO(zra): Implement far branches. Requires loading large immediates.
+  void EmitBranch(ConditionalBranchOp op, Condition cond, Label* label) {
+    if (label->IsBound()) {
+      const int64_t dest = label->Position() - buffer_.Size();
+      ASSERT(CanEncodeImm19BranchOffset(dest));
+      EmitConditionalBranch(op, cond, dest);
+    } else {
+      const int64_t position = buffer_.Size();
+      ASSERT(CanEncodeImm19BranchOffset(position));
+      EmitConditionalBranch(op, cond, label->position_);
+      label->LinkTo(position);
+    }
+  }
+
   void EmitUnconditionalBranchRegOp(UnconditionalBranchRegOp op, Register rn) {
     const int32_t encoding =
         op | (static_cast<int32_t>(rn) << kRnShift);
     Emit(encoding);
   }
 
   void EmitMoveWideOp(MoveWideOp op, Register rd, int32_t imm, int32_t hw_idx,
                       OperandSize sz) {
     ASSERT(Utils::IsUint(16, imm));
     ASSERT((hw_idx >= 0) && (hw_idx <= 3));
@@ skipping 10 matching lines @@
   void EmitLoadStoreReg(LoadStoreRegOp op, Register rt, Address a,
                         OperandSize sz) {
     const int32_t size = Log2OperandSizeBytes(sz);
     const int32_t encoding =
         op | (size << kSzShift) |
         (static_cast<int32_t>(rt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
+  void EmitPCRelOp(PCRelOp op, Register rd, int64_t imm) {
+    ASSERT(Utils::IsInt(21, imm));
+    ASSERT((rd != R31) && (rd != SP));
+    const Register crd = ConcreteRegister(rd);
+    const int32_t loimm = (imm & 0x3) << 29;
+    const int32_t hiimm = ((imm & 0x1ffffc) >> 2) << kImm19Shift;

[regis, 2014/04/11 20:29:21]

Instead of
(imm & 0x1ffffc) >> 2
I would write
(imm >> 2) & kImm19Mask

[zra, 2014/04/11 20:39:59]

Done.

+    const int32_t encoding =
+        op | loimm | hiimm |
+        (static_cast<int32_t>(crd) << kRdShift);
+    Emit(encoding);
+  }
+
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_