Thumb2 Backend: Enable Assembler to encode Thumb2 instructions

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 492 matching lines @@
 const Instr kStrRegFpOffsetPattern =
     al | B26 | Offset | kRegister_fp_Code * B16;
 const Instr kLdrRegFpNegOffsetPattern =
     al | B26 | L | NegOffset | kRegister_fp_Code * B16;
 const Instr kStrRegFpNegOffsetPattern =
     al | B26 | NegOffset | kRegister_fp_Code * B16;
 const Instr kLdrStrInstrTypeMask = 0xffff0000;
 const Instr kLdrStrInstrArgumentMask = 0x0000ffff;
 const Instr kLdrStrOffsetMask = 0x00000fff;
 
+const Instr kThumbLdrPCMask = BH15 | 7 * BH12 | 15 * BH8 | 7 * BH4 | 15 * BH0;
+const Instr kThumbLdrPCPattern = BH15 | 7 * BH12 | BH11 | BH6 | BH4 | 15 * BH0;
 
 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
     : AssemblerBase(isolate, buffer, buffer_size),
       recorded_ast_id_(TypeFeedbackId::None()),
-      positions_recorder_(this) {
+      positions_recorder_(this),
+      thumb_mode_(false) {
   reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
   num_pending_reloc_info_ = 0;
   num_pending_64_bit_reloc_info_ = 0;
   next_buffer_check_ = 0;
   const_pool_blocked_nesting_ = 0;
   no_const_pool_before_ = 0;
   first_const_pool_use_ = -1;
   last_bound_pos_ = 0;
   ClearRecordedAstId();
 }
@@ skipping 240 matching lines @@
 //
 // The linked labels form a link chain by making the branch offset
 // in the instruction steam to point to the previous branch
 // instruction using the same label.
 //
 // The link chain is terminated by a branch offset pointing to the
 // same position.
 
 
 int Assembler::target_at(int pos)  {
+  if (is_thumb_mode()) {
+    return target_at_thumb(pos);
+  }
+
   Instr instr = instr_at(pos);
   if (is_uint24(instr)) {
     // Emitted link to a label, not part of a branch.
     return instr;
   }
   ASSERT((instr & 7*B25) == 5*B25);  // b, bl, or blx imm24
   int imm26 = ((instr & kImm24Mask) << 8) >> 6;
   if ((Instruction::ConditionField(instr) == kSpecialCondition) &&
       ((instr & B24) != 0)) {
     // blx uses bit 24 to encode bit 2 of imm26
     imm26 += 2;
   }
   return pos + kPcLoadDelta + imm26;
 }
 
 
 void Assembler::target_at_put(int pos, int target_pos) {
+  if (is_thumb_mode()) {
+    target_at_put_thumb(pos, target_pos);
+    return;
+  }
+
   Instr instr = instr_at(pos);
   if (is_uint24(instr)) {
     ASSERT(target_pos == pos || target_pos >= 0);
     // Emitted link to a label, not part of a branch.
     // Load the position of the label relative to the generated code object
     // pointer in a register.
 
     // Here are the instructions we need to emit:
     //   For ARMv7: target24 => target16_1:target16_0
     //      movw dst, #target16_0
@@ skipping 501 matching lines @@
     } else {
       // First entry of the link chain points to itself.
       target_pos = pc_offset();
     }
     L->link_to(pc_offset());
   }
 
   // Block the emission of the constant pool, since the branch instruction must
   // be emitted at the pc offset recorded by the label.
   BlockConstPoolFor(1);
+  if (is_thumb_mode()) {
+    return target_pos - (pc_offset() + kThumbPcLoadDelta);
+  }
   return target_pos - (pc_offset() + kPcLoadDelta);
 }
 
 
 // Branch instructions.
 void Assembler::b(int branch_offset, Condition cond) {
+  if (is_thumb_mode()) {
+    ASSERT((branch_offset & 1) == 0);
+    b_thumb(branch_offset, cond);
+    return;
+  }
   ASSERT((branch_offset & 3) == 0);
   int imm24 = branch_offset >> 2;
   ASSERT(is_int24(imm24));
   emit(cond | B27 | B25 | (imm24 & kImm24Mask));
 
   if (cond == al) {
     // Dead code is a good location to emit the constant pool.
     CheckConstPool(false, false);
   }
 }
 
 
 void Assembler::bl(int branch_offset, Condition cond) {
   positions_recorder()->WriteRecordedPositions();
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    ASSERT((branch_offset & 1) == 0);
+    int imm = branch_offset >> 1;
+    emit32(thumb32_mode4(BL_32_IMM) | thumb32_sign_extend_imm24(imm));
+    return;
+  }
   ASSERT((branch_offset & 3) == 0);
   int imm24 = branch_offset >> 2;
   ASSERT(is_int24(imm24));
   emit(cond | B27 | B25 | B24 | (imm24 & kImm24Mask));
 }
 
 
 void Assembler::blx(int branch_offset) {  // v5 and above
   positions_recorder()->WriteRecordedPositions();
+  if (is_thumb_mode()) {
+    ASSERT((branch_offset & 3) == 0);
+    int imm = branch_offset >> 1;
+    emit32(thumb32_mode4(BLX_32_IMM) | thumb32_sign_extend_imm24(imm));
+    return;
+  }
   ASSERT((branch_offset & 1) == 0);
   int h = ((branch_offset & 2) >> 1)*B24;
   int imm24 = branch_offset >> 2;
   ASSERT(is_int24(imm24));
   emit(kSpecialCondition | B27 | B25 | h | (imm24 & kImm24Mask));
 }
 
 
 void Assembler::blx(Register target, Condition cond) {  // v5 and above
   positions_recorder()->WriteRecordedPositions();
   ASSERT(!target.is(pc));
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    emit16(thumb16_mode3(BLX_REG) | thumb16_anyreg_encoding(target));
+    return;
+  }
   emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BLX | target.code());
 }
 
 
 void Assembler::bx(Register target, Condition cond) {  // v5 and above, plus v4t
   positions_recorder()->WriteRecordedPositions();
   ASSERT(!target.is(pc));  // use of pc is actually allowed, but discouraged
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    emit16(thumb16_mode3(BX_REG) | thumb16_anyreg_encoding(target));
+    return;
+  }
   emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BX | target.code());
 }
 
 
 // Data-processing instructions.
 
 void Assembler::and_(Register dst, Register src1, const Operand& src2,
                      SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    and_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   addrmod1(cond | AND | s, src1, dst, src2);
 }
 
 
 void Assembler::eor(Register dst, Register src1, const Operand& src2,
                     SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    eor_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   addrmod1(cond | EOR | s, src1, dst, src2);
 }
 
 
 void Assembler::sub(Register dst, Register src1, const Operand& src2,
                     SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    sub_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   addrmod1(cond | SUB | s, src1, dst, src2);
 }
 
 
 void Assembler::rsb(Register dst, Register src1, const Operand& src2,
                     SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    rsb_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   addrmod1(cond | RSB | s, src1, dst, src2);
 }
 
 
 void Assembler::add(Register dst, Register src1, const Operand& src2,
                     SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    add_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   addrmod1(cond | ADD | s, src1, dst, src2);
 }
 
 
 void Assembler::adc(Register dst, Register src1, const Operand& src2,
                     SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    adc_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   addrmod1(cond | ADC | s, src1, dst, src2);
 }
 
 
 void Assembler::sbc(Register dst, Register src1, const Operand& src2,
                     SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    sbc_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   addrmod1(cond | SBC | s, src1, dst, src2);
 }
 
 
 void Assembler::rsc(Register dst, Register src1, const Operand& src2,
                     SBit s, Condition cond) {
   addrmod1(cond | RSC | s, src1, dst, src2);
 }
 
 
 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
+  if (is_thumb_mode()) {
+    tst_thumb(src1, src2, cond);
+    return;
+  }
   addrmod1(cond | TST | S, src1, r0, src2);
 }
 
 
 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
+  if (is_thumb_mode()) {
+    teq_thumb(src1, src2, cond);
+    return;
+  }
   addrmod1(cond | TEQ | S, src1, r0, src2);
 }
 
 
 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
+  if (is_thumb_mode()) {
+    cmp_thumb(src1, src2, cond);
+    return;
+  }
   addrmod1(cond | CMP | S, src1, r0, src2);
 }
 
 
 void Assembler::cmp_raw_immediate(
     Register src, int raw_immediate, Condition cond) {
   ASSERT(is_uint12(raw_immediate));
   emit(cond | I | CMP | S | src.code() << 16 | raw_immediate);
 }
 
 
 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
+  if (is_thumb_mode()) {
+    cmn_thumb(src1, src2, cond);
+    return;
+  }
   addrmod1(cond | CMN | S, src1, r0, src2);
 }
 
 
 void Assembler::orr(Register dst, Register src1, const Operand& src2,
                     SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    orr_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   addrmod1(cond | ORR | s, src1, dst, src2);
 }
 
 
 void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
   if (dst.is(pc)) {
     positions_recorder()->WriteRecordedPositions();
   }
   // Don't allow nop instructions in the form mov rn, rn to be generated using
   // the mov instruction. They must be generated using nop(int/NopMarkerTypes)
   // or MarkCode(int/NopMarkerTypes) pseudo instructions.
   ASSERT(!(src.is_reg() && src.rm().is(dst) && s == LeaveCC && cond == al));
+  if (is_thumb_mode()) {
+    mov_thumb(dst, src, s, cond);
+    return;
+  }
   addrmod1(cond | MOV | s, r0, dst, src);
 }
 
 
 void Assembler::mov_label_offset(Register dst, Label* label) {
   if (label->is_bound()) {
     mov(dst, Operand(label->pos() + (Code::kHeaderSize - kHeapObjectTag)));
   } else {
     // Emit the link to the label in the code stream followed by extra nop
     // instructions.
@@ skipping 33 matching lines @@
 void Assembler::movw(Register reg, uint32_t immediate, Condition cond) {
   ASSERT(immediate < 0x10000);
   // May use movw if supported, but on unsupported platforms will try to use
   // equivalent rotated immed_8 value and other tricks before falling back to a
   // constant pool load.
   mov(reg, Operand(immediate), LeaveCC, cond);
 }
 
 
 void Assembler::movt(Register reg, uint32_t immediate, Condition cond) {
+  if (is_thumb_mode()) {
+    movt_thumb(reg, immediate, cond);
+    return;
+  }
   emit(cond | 0x34*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate));
 }
 
 
 void Assembler::bic(Register dst, Register src1, const Operand& src2,
                     SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    bic_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   addrmod1(cond | BIC | s, src1, dst, src2);
 }
 
 
 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    mvn_thumb(dst, src, s, cond);
+    return;
+  }
   addrmod1(cond | MVN | s, r0, dst, src);
 }
 
 
 // Multiply instructions.
 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
                     SBit s, Condition cond) {
+  if (is_thumb_mode()) {
+    mla_thumb(dst, src1, src2, srcA, s, cond);
+    return;
+  }
   ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
   emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA,
                     Condition cond) {
+  if (is_thumb_mode()) {
+    mls_thumb(dst, src1, src2, srcA, cond);
+    return;
+  }
   ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
   emit(cond | B22 | B21 | dst.code()*B16 | srcA.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::sdiv(Register dst, Register src1, Register src2,
                      Condition cond) {
+  if (is_thumb_mode()) {
+    sdiv_thumb(dst, src1, src2, cond);
+    return;
+  }
   ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(IsEnabled(SUDIV));
   emit(cond | B26 | B25| B24 | B20 | dst.code()*B16 | 0xf * B12 |
        src2.code()*B8 | B4 | src1.code());
 }
 
 
 void Assembler::mul(Register dst, Register src1, Register src2,
                     SBit s, Condition cond) {
   ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
+  if (is_thumb_mode()) {
+    mul_thumb(dst, src1, src2, s, cond);
+    return;
+  }
   // dst goes in bits 16-19 for this instruction!
   emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::smlal(Register dstL,
                       Register dstH,
                       Register src1,
                       Register src2,
                       SBit s,
                       Condition cond) {
+  if (is_thumb_mode()) {
+    smlal_thumb(dstL, dstH, src1, src2, s, cond);
+    return;
+  }
   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(!dstL.is(dstH));
   emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::smull(Register dstL,
                       Register dstH,
                       Register src1,
                       Register src2,
                       SBit s,
                       Condition cond) {
+  if (is_thumb_mode()) {
+    smull_thumb(dstL, dstH, src1, src2, s, cond);
+    return;
+  }
   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(!dstL.is(dstH));
   emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::umlal(Register dstL,
                       Register dstH,
                       Register src1,
                       Register src2,
                       SBit s,
                       Condition cond) {
+  if (is_thumb_mode()) {
+    umlal_thumb(dstL, dstH, src1, src2, s, cond);
+    return;
+  }
   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(!dstL.is(dstH));
   emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 void Assembler::umull(Register dstL,
                       Register dstH,
                       Register src1,
                       Register src2,
                       SBit s,
                       Condition cond) {
+  if (is_thumb_mode()) {
+    umull_thumb(dstL, dstH, src1, src2, s, cond);
+    return;
+  }
   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
   ASSERT(!dstL.is(dstH));
   emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 |
        src2.code()*B8 | B7 | B4 | src1.code());
 }
 
 
 // Miscellaneous arithmetic instructions.
 void Assembler::clz(Register dst, Register src, Condition cond) {
   // v5 and above.
   ASSERT(!dst.is(pc) && !src.is(pc));
+
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    emit32(BH15 | BH14 | BH13 | BH12 | BH11 | BH9 | BH7 | src.code()*BH0 |
+           B15 | B14 | B13 | B12 | dst.code()*B8 | B7 | src.code());
+    return;
+  }
+
   emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 |
        15*B8 | CLZ | src.code());
 }
 
 
 // Saturating instructions.
 
 // Unsigned saturate.
 void Assembler::usat(Register dst,
                      int satpos,
                      const Operand& src,
                      Condition cond) {
   // v6 and above.
   ASSERT(CpuFeatures::IsSupported(ARMv7));
   ASSERT(!dst.is(pc) && !src.rm_.is(pc));
   ASSERT((satpos >= 0) && (satpos <= 31));
   ASSERT((src.shift_op_ == ASR) || (src.shift_op_ == LSL));
   ASSERT(src.rs_.is(no_reg));
 
   int sh = 0;
   if (src.shift_op_ == ASR) {
       sh = 1;
   }
 
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    emit32(thumb32_mode3(USAT_32_IMM) | sh*BH5 |
+           thumb32_bit_field(src.rm_, dst, src.shift_imm_, satpos));
+    return;
+  }
+
   emit(cond | 0x6*B24 | 0xe*B20 | satpos*B16 | dst.code()*B12 |
        src.shift_imm_*B7 | sh*B6 | 0x1*B4 | src.rm_.code());
 }
 
 
 // Bitfield manipulation instructions.
 
 // Unsigned bit field extract.
 // Extracts #width adjacent bits from position #lsb in a register, and
 // writes them to the low bits of a destination register.
 //   ubfx dst, src, #lsb, #width
 void Assembler::ubfx(Register dst,
                      Register src,
                      int lsb,
                      int width,
                      Condition cond) {
   // v7 and above.
   ASSERT(CpuFeatures::IsSupported(ARMv7));
   ASSERT(!dst.is(pc) && !src.is(pc));
   ASSERT((lsb >= 0) && (lsb <= 31));
   ASSERT((width >= 1) && (width <= (32 - lsb)));
+
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    emit32(thumb32_mode3(UBFX_32_IMM) |
+           thumb32_bit_field(src, dst, lsb, width - 1));
+    return;
+  }
+
   emit(cond | 0xf*B23 | B22 | B21 | (width - 1)*B16 | dst.code()*B12 |
        lsb*B7 | B6 | B4 | src.code());
 }
 
 
 // Signed bit field extract.
 // Extracts #width adjacent bits from position #lsb in a register, and
 // writes them to the low bits of a destination register. The extracted
 // value is sign extended to fill the destination register.
 //   sbfx dst, src, #lsb, #width
 void Assembler::sbfx(Register dst,
                      Register src,
                      int lsb,
                      int width,
                      Condition cond) {
   // v7 and above.
   ASSERT(CpuFeatures::IsSupported(ARMv7));
   ASSERT(!dst.is(pc) && !src.is(pc));
   ASSERT((lsb >= 0) && (lsb <= 31));
   ASSERT((width >= 1) && (width <= (32 - lsb)));
+
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    emit32(thumb32_mode3(SBFX_32_IMM) |
+           thumb32_bit_field(src, dst, lsb, width - 1));
+    return;
+  }
+
   emit(cond | 0xf*B23 | B21 | (width - 1)*B16 | dst.code()*B12 |
        lsb*B7 | B6 | B4 | src.code());
 }
 
 
 // Bit field clear.
 // Sets #width adjacent bits at position #lsb in the destination register
 // to zero, preserving the value of the other bits.
 //   bfc dst, #lsb, #width
 void Assembler::bfc(Register dst, int lsb, int width, Condition cond) {
   // v7 and above.
   ASSERT(CpuFeatures::IsSupported(ARMv7));
   ASSERT(!dst.is(pc));
   ASSERT((lsb >= 0) && (lsb <= 31));
   ASSERT((width >= 1) && (width <= (32 - lsb)));
   int msb = lsb + width - 1;
+
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    emit32(thumb32_mode3(BFC_32_IMM) | thumb32_bit_field(pc, dst, lsb, msb));
+    return;
+  }
+
   emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 | 0xf);
 }
 
 
 // Bit field insert.
 // Inserts #width adjacent bits from the low bits of the source register
 // into position #lsb of the destination register.
 //   bfi dst, src, #lsb, #width
 void Assembler::bfi(Register dst,
                     Register src,
                     int lsb,
                     int width,
                     Condition cond) {
   // v7 and above.
   ASSERT(CpuFeatures::IsSupported(ARMv7));
   ASSERT(!dst.is(pc) && !src.is(pc));
   ASSERT((lsb >= 0) && (lsb <= 31));
   ASSERT((width >= 1) && (width <= (32 - lsb)));
   int msb = lsb + width - 1;
+
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    emit32(thumb32_mode3(BFI_32_IMM) | thumb32_bit_field(src, dst, lsb, msb));
+    return;
+  }
+
   emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 |
        src.code());
 }
 
 
 void Assembler::pkhbt(Register dst,
                       Register src1,
                       const Operand& src2,
                       Condition cond ) {
   // Instruction details available in ARM DDI 0406C.b, A8.8.125.
@@ skipping 123 matching lines @@
   }
   emit(cond | instr | B24 | B21 | fields | 15*B12);
 }
 
 
 // Load/Store instructions.
 void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
   if (dst.is(pc)) {
     positions_recorder()->WriteRecordedPositions();
   }
+
+  if (is_thumb_mode()) {
+    ldr_thumb(dst, src);
+    return;
+  }
+
   addrmod2(cond | B26 | L, dst, src);
 }
 
 
 void Assembler::str(Register src, const MemOperand& dst, Condition cond) {
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    str_thumb(src, dst);
+    return;
+  }
   addrmod2(cond | B26, src, dst);
 }
 
 
 void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) {
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    ldrb_thumb(dst, src);
+    return;
+  }
   addrmod2(cond | B26 | B | L, dst, src);
 }
 
 
 void Assembler::strb(Register src, const MemOperand& dst, Condition cond) {
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    strb_thumb(src, dst);
+    return;
+  }
   addrmod2(cond | B26 | B, src, dst);
 }
 
 
 void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) {
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    ldrh_thumb(dst, src);
+    return;
+  }
   addrmod3(cond | L | B7 | H | B4, dst, src);
 }
 
 
 void Assembler::strh(Register src, const MemOperand& dst, Condition cond) {
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    strh_thumb(src, dst);
+    return;
+  }
   addrmod3(cond | B7 | H | B4, src, dst);
 }
 
 
 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    ldrsb_thumb(dst, src);
+    return;
+  }
   addrmod3(cond | L | B7 | S6 | B4, dst, src);
 }
 
 
 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    ldrsh_thumb(dst, src);
+    return;
+  }
   addrmod3(cond | L | B7 | S6 | H | B4, dst, src);
 }
 
 
 void Assembler::ldrd(Register dst1, Register dst2,
                      const MemOperand& src, Condition cond) {
   ASSERT(IsEnabled(ARMv7));
   ASSERT(src.rm().is(no_reg));
   ASSERT(!dst1.is(lr));  // r14.
   ASSERT_EQ(0, dst1.code() % 2);
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    ASSERT(!src.rm_.is_valid());  // Immediate.
+    ldrd_imm_t1(dst1, dst2, src);
+    return;
+  }
   ASSERT_EQ(dst1.code() + 1, dst2.code());
   addrmod3(cond | B7 | B6 | B4, dst1, src);
 }
 
 
 void Assembler::strd(Register src1, Register src2,
                      const MemOperand& dst, Condition cond) {
   ASSERT(dst.rm().is(no_reg));
   ASSERT(!src1.is(lr));  // r14.
   ASSERT_EQ(0, src1.code() % 2);
+  ASSERT(IsEnabled(ARMv7));
+  if (is_thumb_mode()) {
+    ASSERT(cond == al);
+    ASSERT(!dst.rm_.is_valid());  // Immediate.
+    strd_imm_t1(src1, src2, dst);
+    return;
+  }
   ASSERT_EQ(src1.code() + 1, src2.code());
-  ASSERT(IsEnabled(ARMv7));
   addrmod3(cond | B7 | B6 | B5 | B4, src1, dst);
 }
 
 
 // Preload instructions.
 void Assembler::pld(const MemOperand& address) {
   // Instruction details available in ARM DDI 0406C.b, A8.8.128.
   // 1111(31-28) | 0111(27-24) | U(23) | R(22) | 01(21-20) | Rn(19-16) |
   // 1111(15-12) | imm5(11-07) | type(6-5) | 0(4)| Rm(3-0) |
   ASSERT(address.rm().is(no_reg));
@@ skipping 10 matching lines @@
 }
 
 
 // Load/Store multiple instructions.
 void Assembler::ldm(BlockAddrMode am,
                     Register base,
                     RegList dst,
                     Condition cond) {
   // ABI stack constraint: ldmxx base, {..sp..}  base != sp  is not restartable.
   ASSERT(base.is(sp) || (dst & sp.bit()) == 0);
-
+  if (is_thumb_mode()) {
+    ldm_thumb(am, base, dst, cond);
+    return;
+  }
   addrmod4(cond | B27 | am | L, base, dst);
 
   // Emit the constant pool after a function return implemented by ldm ..{..pc}.
   if (cond == al && (dst & pc.bit()) != 0) {
     // There is a slight chance that the ldm instruction was actually a call,
     // in which case it would be wrong to return into the constant pool; we
     // recognize this case by checking if the emission of the pool was blocked
     // at the pc of the ldm instruction by a mov lr, pc instruction; if this is
     // the case, we emit a jump over the pool.
     CheckConstPool(true, no_const_pool_before_ == pc_offset() - kInstrSize);
   }
 }
 
 
 void Assembler::stm(BlockAddrMode am,
                     Register base,
                     RegList src,
                     Condition cond) {
+  if (is_thumb_mode()) {
+    stm_thumb(am, base, src, cond);
+    return;
+  }
   addrmod4(cond | B27 | am, base, src);
 }
 
 
 // Exception-generating instructions and debugging support.
 // Stops with a non-negative code less than kNumOfWatchedStops support
 // enabling/disabling and a counter feature. See simulator-arm.h .
 void Assembler::stop(const char* msg, Condition cond, int32_t code) {
 #ifndef __arm__
   ASSERT(code >= kDefaultStopCode);
@@ skipping 15 matching lines @@
     bkpt(0);
     bind(&skip);
   } else {
     bkpt(0);
   }
 #endif  // def __arm__
 }
 
 
 void Assembler::bkpt(uint32_t imm16) {  // v5 and above
+  if (is_thumb_mode()) {
+    ASSERT(is_uint8(imm16));
+    emit16(B15 | B13 | B12 | B11 | B10 | B9 | (imm16 & 0xFF));
+    return;
+  }
   ASSERT(is_uint16(imm16));
   emit(al | B24 | B21 | (imm16 >> 4)*B8 | BKPT | (imm16 & 0xf));
 }
 
 
 void Assembler::svc(uint32_t imm24, Condition cond) {
   ASSERT(is_uint24(imm24));
   emit(cond | 15*B24 | imm24);
 }
 
@@ skipping 522 matching lines @@
                      const VmovIndex index,
                      const Register src,
                      const Condition cond) {
   // Dd[index] = Rt
   // Instruction details available in ARM DDI 0406C.b, A8-940.
   // cond(31-28) | 1110(27-24) | 0(23) | opc1=0index(22-21) | 0(20) |
   // Vd(19-16) | Rt(15-12) | 1011(11-8) | D(7) | opc2=00(6-5) | 1(4) | 0000(3-0)
   ASSERT(index.index == 0 || index.index == 1);
   int vd, d;
   dst.split_code(&vd, &d);
+  if (is_thumb_mode() && cond != al) {
+    it_thumb(cond, 1);
+    emit(al | 0xE*B24 | index.index*B21 | vd*B16 | src.code()*B12 | 0xB*B8 |
+         d*B7 | B4);
+    return;
+  }
   emit(cond | 0xE*B24 | index.index*B21 | vd*B16 | src.code()*B12 | 0xB*B8 |
        d*B7 | B4);
 }
 
 
 void Assembler::vmov(const Register dst,
                      const VmovIndex index,
                      const DwVfpRegister src,
                      const Condition cond) {
   // Dd[index] = Rt
@@ skipping 257 matching lines @@
 void Assembler::vneg(const DwVfpRegister dst,
                      const DwVfpRegister src,
                      const Condition cond) {
   // Instruction details available in ARM DDI 0406C.b, A8-968.
   // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) |
   // 101(11-9) | sz=1(8) | 0(7) | 1(6) | M(5) | 0(4) | Vm(3-0)
   int vd, d;
   dst.split_code(&vd, &d);
   int vm, m;
   src.split_code(&vm, &m);
-
+  if (is_thumb_mode() && cond != al) {
+    it_thumb(cond, 1);
+    emit(al | 0x1D*B23 | d*B22 | 0x3*B20 | B16 | vd*B12 | 0x5*B9 | B8 | B6 |
+         m*B5 | vm);
+    return;
+  }
   emit(cond | 0x1D*B23 | d*B22 | 0x3*B20 | B16 | vd*B12 | 0x5*B9 | B8 | B6 |
        m*B5 | vm);
 }
 
 
 void Assembler::vabs(const DwVfpRegister dst,
                      const DwVfpRegister src,
                      const Condition cond) {
   // Instruction details available in ARM DDI 0406C.b, A8-524.
   // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0000(19-16) | Vd(15-12) |
@@ skipping 231 matching lines @@
 
 
 // Pseudo instructions.
 void Assembler::nop(int type) {
   // ARMv6{K/T2} and v7 have an actual NOP instruction but it serializes
   // some of the CPU's pipeline and has to issue. Older ARM chips simply used
   // MOV Rx, Rx as NOP and it performs better even in newer CPUs.
   // We therefore use MOV Rx, Rx, even on newer CPUs, and use Rx to encode
   // a type.
   ASSERT(0 <= type && type <= 14);  // mov pc, pc isn't a nop.
+  if (is_thumb_mode()) {
+    uint16_t d = type >> 3;
+    emit16(4*B12 | 6*B8 | d*B7 | type*B3 | (type & 7));
+    return;
+  }
   emit(al | 13*B21 | type*B12 | type);
 }
 
 
 bool Assembler::IsMovT(Instr instr) {
   instr &= ~(((kNumberOfConditions - 1) << 28) |  // Mask off conditions
              ((kNumRegisters-1)*B12) |            // mask out register
              EncodeMovwImmediate(0xFFFF));        // mask out immediate value
   return instr == 0x34*B20;
 }
 
 
 bool Assembler::IsMovW(Instr instr) {
   instr &= ~(((kNumberOfConditions - 1) << 28) |  // Mask off conditions
              ((kNumRegisters-1)*B12) |            // mask out destination
              EncodeMovwImmediate(0xFFFF));        // mask out immediate value
   return instr == 0x30*B20;
 }
 
 
+bool Assembler::IsMovTThumb(Instr instr) {
+  return ((instr & ~MOVW_THUMB_IMM_MASK) == (MOVW_THUMB_MASK | BH7));
+}
+
+
+bool Assembler::IsMovWThumb(Instr instr) {
+  return ((instr & ~MOVW_THUMB_IMM_MASK) == MOVW_THUMB_MASK);
+}
+
+
 bool Assembler::IsNop(Instr instr, int type) {
   ASSERT(0 <= type && type <= 14);  // mov pc, pc isn't a nop.
   // Check for mov rx, rx where x = type.
   return instr == (al | 13*B21 | type*B12 | type);
 }
 
 
 bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
   uint32_t dummy1;
   uint32_t dummy2;
@@ skipping 271 matching lines @@
     RecordConstPool(size);
 
     // Emit jump over constant pool if necessary.
     Label after_pool;
     if (require_jump) {
       b(&after_pool);
     }
 
     // Put down constant pool marker "Undefined instruction".
     // The data size helps disassembly know what to print.
-    emit(kConstantPoolMarker |
-         EncodeConstantPoolLength(size_after_marker / kPointerSize));
+    if (is_thumb_mode()) {
+      emit32(kConstantPoolMarker |
+             EncodeConstantPoolLength(size_after_marker / kPointerSize));
+    } else {
+      emit(kConstantPoolMarker |
+           EncodeConstantPoolLength(size_after_marker / kPointerSize));
+    }
 
     if (require_64_bit_align) {
       emit(kConstantPoolMarker);
     }
 
     // Emit 64-bit constant pool entries first: their range is smaller than
     // 32-bit entries.
     for (int i = 0; i < num_pending_reloc_info_; i++) {
       RelocInfo& rinfo = pending_reloc_info_[i];
 
@@ skipping 27 matching lines @@
       ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
              rinfo.rmode() != RelocInfo::POSITION &&
              rinfo.rmode() != RelocInfo::STATEMENT_POSITION &&
              rinfo.rmode() != RelocInfo::CONST_POOL);
 
       if (rinfo.rmode() == RelocInfo::NONE64) {
         // 64-bit values emitted earlier.
         continue;
       }
 
+      if (is_thumb_mode()) {
+        Instr instr = thumb32_instr_at(rinfo.pc());
+        int thumb_ldr_delta = 2;
+        if ((reinterpret_cast<int>(rinfo.pc()) & 3) == 0) {
+          thumb_ldr_delta = 4;
+        }
+        int delta = pc_ - rinfo.pc() - thumb_ldr_delta;
+        ASSERT(is_uint12(delta));
+        instr &= ~kOff12Mask;
+        instr |= delta;
+        thumb32_instr_at_put(rinfo.pc(), instr);
+        set_arm_mode();
+        emit(rinfo.data());
+        set_thumb_mode();
+        continue;
+      }
+
       Instr instr = instr_at(rinfo.pc());
 
       // 64-bit loads shouldn't get here.
       ASSERT(!IsVldrDPcImmediateOffset(instr));
 
       int delta = pc_ - rinfo.pc() - kPcLoadDelta;
       // 0 is the smallest delta:
       //   ldr rd, [pc, #0]
       //   constant pool marker
       //   data
@@ skipping 22 matching lines @@
 
   // Since a constant pool was just emitted, move the check offset forward by
   // the standard interval.
   next_buffer_check_ = pc_offset() + kCheckPoolInterval;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM