Thumb2 Backend: Branch, load, store, misc. instruction encoding methods

src/arm/assembler-arm.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 806 matching lines @@
 
   // Insert the smallest number of nop instructions
   // possible to align the pc offset to a multiple
   // of m. m must be a power of 2 (>= 4).
   void Align(int m);
   // Aligns code to something that's optimal for a jump target for the platform.
   void CodeTargetAlign();
 
   // Branch instructions
   void b(int branch_offset, Condition cond = al);
+  void b_thumb(int branch_offset, Condition cond);
   void bl(int branch_offset, Condition cond = al);
   void blx(int branch_offset);  // v5 and above
   void blx(Register target, Condition cond = al);  // v5 and above
   void bx(Register target, Condition cond = al);  // v5 and above, plus v4t
 
   // Convenience branch instructions using labels
   void b(Label* L, Condition cond = al)  {
     b(branch_offset(L, cond == al), cond);
   }
   void b(Condition cond, Label* L)  { b(branch_offset(L, cond == al), cond); }
@@ skipping 179 matching lines @@
                   uint32_t i, uint32_t imm3, uint32_t imm8);
   void mvn_reg_t2(Register dst, const Operand& src,
                   SBit s, Condition cond);
   void mvn_thumb(Register dst, const Operand& src,
                  SBit s, Condition cond);
 
   // Multiply instructions
 
   void mla(Register dst, Register src1, Register src2, Register srcA,
            SBit s = LeaveCC, Condition cond = al);
+  void mla_thumb(Register dst, Register src1, Register src2, Register srcA,
+                 SBit s, Condition cond);
 
   void mls(Register dst, Register src1, Register src2, Register srcA,
            Condition cond = al);
+  void mls_thumb(Register dst, Register src1, Register src2, Register srcA,
+                 Condition cond);
 
   void sdiv(Register dst, Register src1, Register src2,
             Condition cond = al);
+  void sdiv_thumb(Register dst, Register src1, Register src2,
+                  Condition cond);
 
   void mul(Register dst, Register src1, Register src2,
            SBit s = LeaveCC, Condition cond = al);
   void mul_t2(Register dst, Register src1, Register src2,
               SBit s, Condition cond);
   void mul_thumb(Register dst, Register src1, Register src2,
                  SBit s, Condition cond);
 
   void smlal(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
+  void smlal_thumb(Register dstL, Register dstH, Register src1, Register src2,
+                   SBit s, Condition cond);
 
   void smull(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
+  void smull_thumb(Register dstL, Register dstH, Register src1, Register src2,
+                   SBit s, Condition cond);
 
   void umlal(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
+  void umlal_thumb(Register dstL, Register dstH, Register src1, Register src2,
+                   SBit s, Condition cond);
 
   void umull(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
+  void umull_thumb(Register dstL, Register dstH, Register src1, Register src2,
+                   SBit s, Condition cond);
 
   // Miscellaneous arithmetic instructions
 
   void clz(Register dst, Register src, Condition cond = al);  // v5 and above
 
   // Saturating instructions. v6 and above.
 
   // Unsigned saturate.
   //
   // Saturate an optionally shifted signed value to an unsigned range.
@@ skipping 37 matching lines @@
 
   void uxtb16(Register dst, const Operand& src, Condition cond = al);
 
   // Status register access instructions
 
   void mrs(Register dst, SRegister s, Condition cond = al);
   void msr(SRegisterFieldMask fields, const Operand& src, Condition cond = al);
 
   // Load/Store instructions
   void ldr(Register dst, const MemOperand& src, Condition cond = al);
+  void ldr_thumb(Register dst, const MemOperand& src);
+  void ldr_thumb_immediate(Register dst, const MemOperand& src);
+  void ldr_thumb_register(Register dst, const MemOperand& src);
+
   void str(Register src, const MemOperand& dst, Condition cond = al);
+  void str_thumb(Register src, const MemOperand& dst);
+  void str_thumb_register(Register src, const MemOperand& dst);
+  void str_thumb_immediate(Register src, const MemOperand& dst);
+
   void ldrb(Register dst, const MemOperand& src, Condition cond = al);
+  void ldrb_thumb_immediate(Register dst, const MemOperand& src);
+  void ldrb_thumb_register(Register dst, const MemOperand& src);
+  void ldrb_thumb(Register dst, const MemOperand& src);
+
   void strb(Register src, const MemOperand& dst, Condition cond = al);
+  void strb_thumb_immediate(Register src, const MemOperand& dst);
+  void strb_thumb_register(Register src, const MemOperand& dst);
+  void strb_thumb(Register src, const MemOperand& dst);
+
   void ldrh(Register dst, const MemOperand& src, Condition cond = al);
+  void ldrh_thumb_immediate(Register dst, const MemOperand& src);
+  void ldrh_thumb_register(Register dst, const MemOperand& src);
+  void ldrh_thumb(Register dst, const MemOperand& src);
+
   void strh(Register src, const MemOperand& dst, Condition cond = al);
+  void strh_thumb_immediate(Register src, const MemOperand& dst);  // 4_4
+  void strh_thumb_register(Register src, const MemOperand& dst);   // 4_1
+  void strh_thumb(Register src, const MemOperand& dst);
+
   void ldrsb(Register dst, const MemOperand& src, Condition cond = al);
+  void ldrsb_thumb_immediate(Register dst, const MemOperand& src);
+  void ldrsb_thumb_register(Register dst, const MemOperand& src);
+  void ldrsb_thumb(Register dst, const MemOperand& src);
+
   void ldrsh(Register dst, const MemOperand& src, Condition cond = al);
+  void ldrsh_thumb(Register dst, const MemOperand& src);
+  void ldrsh_thumb_immediate(Register dst, const MemOperand& src);
+  void ldrsh_thumb_register(Register dst, const MemOperand& src);
+
   void ldrd(Register dst1,
             Register dst2,
             const MemOperand& src, Condition cond = al);
   void ldrd_imm_t1(Register dst1,
                    Register dst2,
                    const MemOperand& src);
   void strd(Register src1,
             Register src2,
             const MemOperand& dst, Condition cond = al);
   void strd_imm_t1(Register src1,
                    Register src2,
                    const MemOperand& dst);
 
   // Preload instructions
   void pld(const MemOperand& address);
 
   // Load/Store multiple instructions
   void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al);
+  void ldm_thumb(BlockAddrMode am, Register base, RegList dst, Condition cond);
+
   void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al);
+  void stm_thumb(BlockAddrMode am, Register base, RegList dst, Condition cond);
 
   // Exception-generating instructions and debugging support
   void stop(const char* msg,
             Condition cond = al,
             int32_t code = kDefaultStopCode);
 
   void bkpt(uint32_t imm16);  // v5 and above
   void svc(uint32_t imm24, Condition cond = al);
 
   // Coprocessor instructions
@@ skipping 238 matching lines @@
   void pop() {
     add(sp, sp, Operand(kPointerSize));
   }
 
   // Jump unconditionally to given label.
   void jmp(Label* L) { b(L, al); }
 
   void it_thumb(Condition cond, int num_instr, bool cond2 = false,
                 bool cond3 = false, bool cond4 = false);
   inline void emit_it(Condition cond);
+  void ldr_pc_thumb(Register dst, const Operand& src);
 
   static bool use_immediate_embedded_pointer_loads(
       const Assembler* assembler) {
     return CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS) &&
         (assembler == NULL || !assembler->predictable_code_size());
   }
 
   // Check the code size generated from label to here.
   int SizeOfCodeGeneratedSince(Label* label) {
     return pc_offset() - label->pos();
@@ skipping 254 matching lines @@
   void GrowBuffer();
   inline void emit(Instr x);
   inline void emit16(Instr16 x, bool check_buffer = true);
   inline void emit32(Instr x);  // proper half-word order for thumb
 
   // 32-bit immediate values
   void move_32_bit_immediate(Condition cond,
                              Register rd,
                              SBit s,
                              const Operand& x);
+  void move_32_bit_immediate_thumb(Register rd,
+                                   SBit s,
+                                   const Operand& x,
+                                   Condition cond = al);
 
   // Instruction generation
   void addrmod1(Instr instr, Register rn, Register rd, const Operand& x);
   void addrmod2(Instr instr, Register rd, const MemOperand& x);
   void addrmod3(Instr instr, Register rd, const MemOperand& x);
   void addrmod4(Instr instr, Register rn, RegList rl);
   void addrmod5(Instr instr, CRegister crd, const MemOperand& x);
 
   Instr16 thumb16_mode1(ThumbMode1Opcode16 op);  // A6.2.1 -> mode1
   Instr16 thumb16_mode2(ThumbMode2Opcode16 op);  // A6.2.2 -> mode2
@@ skipping 127 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM_ASSEMBLER_ARM_H_