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Issue 23526069: Refactor back edge table related code into a new class. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 3 months ago
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1 1
2 // Copyright 2011 the V8 project authors. All rights reserved. 2 // Copyright 2011 the V8 project authors. All rights reserved.
3 // Redistribution and use in source and binary forms, with or without 3 // Redistribution and use in source and binary forms, with or without
4 // modification, are permitted provided that the following conditions are 4 // modification, are permitted provided that the following conditions are
5 // met: 5 // met:
6 // 6 //
7 // * Redistributions of source code must retain the above copyright 7 // * Redistributions of source code must retain the above copyright
8 // notice, this list of conditions and the following disclaimer. 8 // notice, this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above 9 // * Redistributions in binary form must reproduce the above
10 // copyright notice, this list of conditions and the following 10 // copyright notice, this list of conditions and the following
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71 call_address >= prev_call_address + patch_size()); 71 call_address >= prev_call_address + patch_size());
72 ASSERT(call_address + patch_size() <= code->instruction_end()); 72 ASSERT(call_address + patch_size() <= code->instruction_end());
73 73
74 #ifdef DEBUG 74 #ifdef DEBUG
75 prev_call_address = call_address; 75 prev_call_address = call_address;
76 #endif 76 #endif
77 } 77 }
78 } 78 }
79 79
80 80
81 // This structure comes from FullCodeGenerator::EmitBackEdgeBookkeeping.
82 // The back edge bookkeeping code matches the pattern:
83 //
84 // sltu at, sp, t0 / slt at, a3, zero_reg (in case of count based interrupts)
85 // beq at, zero_reg, ok
86 // lui t9, <interrupt stub address> upper
87 // ori t9, <interrupt stub address> lower
88 // jalr t9
89 // nop
90 // ok-label ----- pc_after points here
91 //
92 // We patch the code to the following form:
93 //
94 // addiu at, zero_reg, 1
95 // beq at, zero_reg, ok ;; Not changed
96 // lui t9, <on-stack replacement address> upper
97 // ori t9, <on-stack replacement address> lower
98 // jalr t9 ;; Not changed
99 // nop ;; Not changed
100 // ok-label ----- pc_after points here
101
102 void Deoptimizer::PatchInterruptCodeAt(Code* unoptimized_code,
103 Address pc_after,
104 Code* replacement_code) {
105 static const int kInstrSize = Assembler::kInstrSize;
106 // Replace the sltu instruction with load-imm 1 to at, so beq is not taken.
107 CodePatcher patcher(pc_after - 6 * kInstrSize, 1);
108 patcher.masm()->addiu(at, zero_reg, 1);
109 // Replace the stack check address in the load-immediate (lui/ori pair)
110 // with the entry address of the replacement code.
111 Assembler::set_target_address_at(pc_after - 4 * kInstrSize,
112 replacement_code->entry());
113
114 unoptimized_code->GetHeap()->incremental_marking()->RecordCodeTargetPatch(
115 unoptimized_code, pc_after - 4 * kInstrSize, replacement_code);
116 }
117
118
119 void Deoptimizer::RevertInterruptCodeAt(Code* unoptimized_code,
120 Address pc_after,
121 Code* interrupt_code) {
122 static const int kInstrSize = Assembler::kInstrSize;
123 // Restore the sltu instruction so beq can be taken again.
124 CodePatcher patcher(pc_after - 6 * kInstrSize, 1);
125 patcher.masm()->slt(at, a3, zero_reg);
126 // Restore the original call address.
127 Assembler::set_target_address_at(pc_after - 4 * kInstrSize,
128 interrupt_code->entry());
129
130 interrupt_code->GetHeap()->incremental_marking()->RecordCodeTargetPatch(
131 unoptimized_code, pc_after - 4 * kInstrSize, interrupt_code);
132 }
133
134
135 #ifdef DEBUG
136 Deoptimizer::InterruptPatchState Deoptimizer::GetInterruptPatchState(
137 Isolate* isolate,
138 Code* unoptimized_code,
139 Address pc_after) {
140 static const int kInstrSize = Assembler::kInstrSize;
141 ASSERT(Assembler::IsBeq(Assembler::instr_at(pc_after - 5 * kInstrSize)));
142 if (Assembler::IsAddImmediate(
143 Assembler::instr_at(pc_after - 6 * kInstrSize))) {
144 Code* osr_builtin =
145 isolate->builtins()->builtin(Builtins::kOnStackReplacement);
146 ASSERT(reinterpret_cast<uint32_t>(
147 Assembler::target_address_at(pc_after - 4 * kInstrSize)) ==
148 reinterpret_cast<uint32_t>(osr_builtin->entry()));
149 return PATCHED_FOR_OSR;
150 } else {
151 // Get the interrupt stub code object to match against from cache.
152 Code* interrupt_builtin =
153 isolate->builtins()->builtin(Builtins::kInterruptCheck);
154 ASSERT(reinterpret_cast<uint32_t>(
155 Assembler::target_address_at(pc_after - 4 * kInstrSize)) ==
156 reinterpret_cast<uint32_t>(interrupt_builtin->entry()));
157 return NOT_PATCHED;
158 }
159 }
160 #endif // DEBUG
161
162
163 void Deoptimizer::FillInputFrame(Address tos, JavaScriptFrame* frame) { 81 void Deoptimizer::FillInputFrame(Address tos, JavaScriptFrame* frame) {
164 // Set the register values. The values are not important as there are no 82 // Set the register values. The values are not important as there are no
165 // callee saved registers in JavaScript frames, so all registers are 83 // callee saved registers in JavaScript frames, so all registers are
166 // spilled. Registers fp and sp are set to the correct values though. 84 // spilled. Registers fp and sp are set to the correct values though.
167 85
168 for (int i = 0; i < Register::kNumRegisters; i++) { 86 for (int i = 0; i < Register::kNumRegisters; i++) {
169 input_->SetRegister(i, i * 4); 87 input_->SetRegister(i, i * 4);
170 } 88 }
171 input_->SetRegister(sp.code(), reinterpret_cast<intptr_t>(frame->sp())); 89 input_->SetRegister(sp.code(), reinterpret_cast<intptr_t>(frame->sp()));
172 input_->SetRegister(fp.code(), reinterpret_cast<intptr_t>(frame->fp())); 90 input_->SetRegister(fp.code(), reinterpret_cast<intptr_t>(frame->fp()));
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448 366
449 void FrameDescription::SetCallerFp(unsigned offset, intptr_t value) { 367 void FrameDescription::SetCallerFp(unsigned offset, intptr_t value) {
450 SetFrameSlot(offset, value); 368 SetFrameSlot(offset, value);
451 } 369 }
452 370
453 371
454 #undef __ 372 #undef __
455 373
456 374
457 } } // namespace v8::internal 375 } } // namespace v8::internal
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