[SubZero] lower float and double constants for MIPS

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 3403 matching lines @@
     OstreamLocker L(Ctx);
     for (const VariableDeclaration *Var : Vars) {
       if (getFlags().matchTranslateOnly(Var->getName(), 0)) {
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 
+namespace {
+template <typename T> struct ConstantPoolEmitterTraits;
+
+static_assert(sizeof(uint64_t) == 8,
+              "uint64_t is supposed to be 8 bytes wide.");
+
+// TODO(jaydeep.patil): implement the following when implementing constant
+// randomization:
+//  * template <> struct ConstantPoolEmitterTraits<uint8_t>
+//  * template <> struct ConstantPoolEmitterTraits<uint16_t>
+//  * template <> struct ConstantPoolEmitterTraits<uint32_t>
+template <> struct ConstantPoolEmitterTraits<float> {
+  using ConstantType = ConstantFloat;
+  static constexpr Type IceType = IceType_f32;
+  // AsmTag and TypeName can't be constexpr because llvm::StringRef is unhappy
+  // about them being constexpr.
+  static const char AsmTag[];
+  static const char TypeName[];
+  static uint64_t bitcastToUint64(float Value) {
+    static_assert(sizeof(Value) == sizeof(uint32_t),
+                  "Float should be 4 bytes.");
+    const uint32_t IntValue = Utils::bitCopy<uint32_t>(Value);
+    return static_cast<uint64_t>(IntValue);
+  }
+};
+const char ConstantPoolEmitterTraits<float>::AsmTag[] = ".word";
+const char ConstantPoolEmitterTraits<float>::TypeName[] = "f32";
+
+template <> struct ConstantPoolEmitterTraits<double> {
+  using ConstantType = ConstantDouble;
+  static constexpr Type IceType = IceType_f64;
+  static const char AsmTag[];
+  static const char TypeName[];
+  static uint64_t bitcastToUint64(double Value) {
+    static_assert(sizeof(double) == sizeof(uint64_t),
+                  "Double should be 8 bytes.");
+    return Utils::bitCopy<uint64_t>(Value);
+  }
+};
+const char ConstantPoolEmitterTraits<double>::AsmTag[] = ".word";

[Jim Stichnoth, 2016/09/19 20:50:14]

I was wondering about the use of ".word" for both types here, while ARM does
.long/.quad.  (Also that ARM's emitConstant() is very clean without needing to
test Traits::IceType.)

It seems that llvm-mc does support .quad.  This asm line:
	.quad   0x123456789abcdef0
assembles/objdumps to:
   0:	9abcdef0 	lwr	gp,-8464(s5)
   4:	12345678 	beq	s1,s4,159e8 <test_nans+0x15938>

I'm not sure about endian-ness here, but looking at the raw .o file, I see
f0debc9a78563412 (where the lower address contains 0xf0 and the higher address
contains 0x12.

So I'm wondering if this needs to diverge from the more elegant ARM32 version?

[jaydeep.patil, 2016/09/20 07:28:27]

Done.

+const char ConstantPoolEmitterTraits<double>::TypeName[] = "f64";
+
+template <typename T>
+void emitConstant(
+    Ostream &Str,
+    const typename ConstantPoolEmitterTraits<T>::ConstantType *Const) {
+  if (!BuildDefs::dump())
+    return;
+  using Traits = ConstantPoolEmitterTraits<T>;
+  Str << Const->getLabelName();
+  T Value = Const->getValue();
+  if (Traits::IceType == IceType_f64) {
+    uint64_t BitValue = Traits::bitcastToUint64(Value);
+    uint32_t BitValueHi = (BitValue >> 32) & 0xffffffff;
+    uint32_t BitValueLo = BitValue & 0xffffffff;
+    Str << ":\n\t" << Traits::AsmTag << "\t0x";
+    Str.write_hex(BitValueHi);
+    Str << "\n\t" << Traits::AsmTag << "\t0x";
+    Str.write_hex(BitValueLo);
+  } else {
+    Str << ":\n\t" << Traits::AsmTag << "\t0x";
+    Str.write_hex(Traits::bitcastToUint64(Value));
+  }
+  Str << "\t/* " << Traits::TypeName << " " << Value << " */\n";
+}
+
+template <typename T> void emitConstantPool(GlobalContext *Ctx) {
+  if (!BuildDefs::dump())
+    return;
+  using Traits = ConstantPoolEmitterTraits<T>;
+  static constexpr size_t MinimumAlignment = 4;
+  SizeT Align = std::max(MinimumAlignment, typeAlignInBytes(Traits::IceType));
+  assert((Align % 4) == 0 && "Constants should be aligned");
+  Ostream &Str = Ctx->getStrEmit();
+  ConstantList Pool = Ctx->getConstantPool(Traits::IceType);
+  Str << "\t.section\t.rodata.cst" << Align << ",\"aM\",%progbits," << Align
+      << "\n"
+      << "\t.align\t" << (Align == 4 ? 2 : 3) << "\n";
+  if (getFlags().getReorderPooledConstants()) {
+    // TODO(jaydeep.patil): add constant pooling.
+    UnimplementedError(getFlags());
+  }
+  for (Constant *C : Pool) {
+    if (!C->getShouldBePooled()) {
+      continue;
+    }
+    emitConstant<T>(Str, llvm::dyn_cast<typename Traits::ConstantType>(C));
+  }
+}
+} // end of anonymous namespace
+
 void TargetDataMIPS32::lowerConstants() {
   if (getFlags().getDisableTranslation())
     return;
+  switch (getFlags().getOutFileType()) {
+  case FT_Elf: {
+    ELFObjectWriter *Writer = Ctx->getObjectWriter();
+    Writer->writeConstantPool<ConstantFloat>(IceType_f32);
+    Writer->writeConstantPool<ConstantDouble>(IceType_f64);
+  } break;
+  case FT_Asm:
+  case FT_Iasm: {
+    OstreamLocker _(Ctx);
+    emitConstantPool<float>(Ctx);
+    emitConstantPool<double>(Ctx);
+    break;
+  }
+  }
 }
 
 void TargetDataMIPS32::lowerJumpTables() {
   if (getFlags().getDisableTranslation())
     return;
 }
 
 // Helper for legalize() to emit the right code to lower an operand to a
 // register of the appropriate type.
 Variable *TargetMIPS32::copyToReg(Operand *Src, RegNumT RegNum) {
@@ skipping 230 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice