Subzero, MIPS32: Encoding of FP comparison instructions

src/IceAssemblerMIPS32.cpp

 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 236 matching lines @@
   const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
   const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName);
 
   Opcode |= Rs << 21;
   Opcode |= Rt << 16;
   Opcode |= Rd << 11;
 
   emitInst(Opcode);
 }
 
+void AssemblerMIPS32::emitCOP1Fcmp(IValueT Opcode, FPInstDataFormat Format,
+                                   const Operand *OpFs, const Operand *OpFt,
+                                   IValueT CC, const char *InsnName) {
+  const IValueT Fs = encodeFPRegister(OpFs, "Fs", InsnName);
+  const IValueT Ft = encodeFPRegister(OpFt, "Ft", InsnName);
+
+  Opcode |= CC << 8;
+  Opcode |= Fs << 11;
+  Opcode |= Ft << 16;
+  Opcode |= Format << 21;
+
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::emitCOP1FmtFsFd(IValueT Opcode, FPInstDataFormat Format,
                                       const Operand *OpFd, const Operand *OpFs,
                                       const char *InsnName) {
   const IValueT Fd = encodeFPRegister(OpFd, "Fd", InsnName);
   const IValueT Fs = encodeFPRegister(OpFs, "Fs", InsnName);
 
   Opcode |= Fd << 6;
   Opcode |= Fs << 11;
   Opcode |= Format << 21;
 
@@ skipping 97 matching lines @@
   if (TargetLabel->isBound()) {
     const int32_t Dest = TargetLabel->getPosition() - Buffer.size();
     emitBr(CondMIPS32::AL, OpRsNone, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(CondMIPS32::AL, OpRsNone, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
+void AssemblerMIPS32::c_eq_d(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000032;
+  emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.eq.d");
+}
+
+void AssemblerMIPS32::c_eq_s(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000032;
+  emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.eq.s");
+}
+
+void AssemblerMIPS32::c_ole_d(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000036;
+  emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.ole.d");
+}
+
+void AssemblerMIPS32::c_ole_s(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000036;
+  emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.ole.s");
+}
+
+void AssemblerMIPS32::c_olt_d(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000034;
+  emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.olt.d");
+}
+
+void AssemblerMIPS32::c_olt_s(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000034;
+  emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.olt.s");
+}
+
+void AssemblerMIPS32::c_ueq_d(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000033;
+  emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.ueq.d");
+}
+
+void AssemblerMIPS32::c_ueq_s(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000033;
+  emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.ueq.s");
+}
+
+void AssemblerMIPS32::c_ule_d(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000037;
+  emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.ule.d");
+}
+
+void AssemblerMIPS32::c_ule_s(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000037;
+  emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.ule.s");
+}
+
+void AssemblerMIPS32::c_ult_d(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000035;
+  emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.ult.d");
+}
+
+void AssemblerMIPS32::c_ult_s(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000035;
+  emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.ult.s");
+}
+
+void AssemblerMIPS32::c_un_d(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000031;
+  emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.un.d");
+}
+
+void AssemblerMIPS32::c_un_s(const Operand *OpFs, const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000031;
+  emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
+               "c.un.s");
+}
+
 void AssemblerMIPS32::cvt_d_l(const Operand *OpFd, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000021;
   emitCOP1FmtFsFd(Opcode, Long, OpFd, OpFs, "cvt.d.l");
 }
 
 void AssemblerMIPS32::cvt_d_s(const Operand *OpFd, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000021;
   emitCOP1FmtFsFd(Opcode, SinglePrecision, OpFd, OpFs, "cvt.d.s");
 }
 
@@ skipping 106 matching lines @@
       Opcode |= Rt << 16;
       Opcode |= Rd << 11;
       emitInst(Opcode);
       break;
     }
     default: { UnimplementedError(getFlags()); }
     }
   }
 }
 
+void AssemblerMIPS32::movf(const Operand *OpRd, const Operand *OpRs,
+                           const Operand *OpCc) {
+  IValueT Opcode = 0x00000001;
+  const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movf");
+  const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf");
+  OperandMIPS32FCC::FCC Cc = OperandMIPS32FCC::FCC0;
+  if (const auto *OpFCC = llvm::dyn_cast<OperandMIPS32FCC>(OpCc)) {
+    Cc = OpFCC->getFCC();
+  }
+  IValueT InstEncodingFalse = 0;

[Jim Stichnoth, 2016/09/20 00:09:23]

const or constexpr

[obucinac, 2016/09/20 13:24:52]

Done.

+  Opcode |= Rd << 11;
+  Opcode |= InstEncodingFalse << 16;
+  Opcode |= Cc << 18;
+  Opcode |= Rs << 21;
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::movn_d(const Operand *OpFd, const Operand *OpFs,
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000013;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.d");
 }
 
 void AssemblerMIPS32::movn_s(const Operand *OpFd, const Operand *OpFs,
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000013;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s");
 }
 
+void AssemblerMIPS32::movt(const Operand *OpRd, const Operand *OpRs,
+                           const Operand *OpCc) {
+  IValueT Opcode = 0x00000001;
+  const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movf");
+  const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf");
+  OperandMIPS32FCC::FCC Cc = OperandMIPS32FCC::FCC0;
+  if (const auto *OpFCC = llvm::dyn_cast<OperandMIPS32FCC>(OpCc)) {
+    Cc = OpFCC->getFCC();
+  }
+  IValueT InstEncodingTrue = 1;

[Jim Stichnoth, 2016/09/20 00:09:23]

const or constexpr

[obucinac, 2016/09/20 13:24:52]

Done.

+  Opcode |= Rd << 11;
+  Opcode |= InstEncodingTrue << 16;
+  Opcode |= Cc << 18;
+  Opcode |= Rs << 21;
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::movz_d(const Operand *OpFd, const Operand *OpFs,
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000012;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movz.d");
 }
 
 void AssemblerMIPS32::movz_s(const Operand *OpFd, const Operand *OpFs,
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000012;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movz.s");
@@ skipping 232 matching lines @@
     emitBr(Cond, OpRs, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice