Subzero, MIPS32: nacl-other-intrinsics-mips merged to original file

tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll

 ; This tests the NaCl intrinsics not related to atomic operations.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 --sandbox -i %s --args -O2 \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 --sandbox -i %s --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
@@ skipping 126 matching lines @@
 }
 ; CHECK-LABEL: test_setjmplongjmp
 ; CHECK: call {{.*}} R_{{.*}} setjmp
 ; CHECK: call {{.*}} R_{{.*}} longjmp
 ; CHECKO2REM-LABEL: test_setjmplongjmp
 ; CHECKO2REM: call {{.*}} R_{{.*}} setjmp
 ; CHECKO2REM: call {{.*}} R_{{.*}} longjmp
 ; ARM32-LABEL: test_setjmplongjmp
 ; ARM32: bl {{.*}} setjmp
 ; ARM32: bl {{.*}} longjmp
+; MIPS32-LABEL: test_setjmplongjmp
+; MIPS32: jal {{.*}} setjmp
+; MIPS32: jal {{.*}} longjmp
 
 define internal i32 @test_setjmp_unused(i32 %iptr_env, i32 %i_other) {
 entry:
   %env = inttoptr i32 %iptr_env to i8*
   %i = call i32 @llvm.nacl.setjmp(i8* %env)
   ret i32 %i_other
 }
 ; Don't consider setjmp side-effect free, so it's not eliminated if
 ; result unused.
 ; CHECKO2REM-LABEL: test_setjmp_unused
 ; CHECKO2REM: call {{.*}} R_{{.*}} setjmp
+; MIPS32-LABEL: test_setjmp_unused
+; MIPS32: jal {{.*}} setjmp
 
 define internal float @test_sqrt_float(float %x, i32 %iptr) {
 entry:
   %r = call float @llvm.sqrt.f32(float %x)
   %r2 = call float @llvm.sqrt.f32(float %r)
   %r3 = call float @llvm.sqrt.f32(float -0.0)
   %r4 = fadd float %r2, %r3
   ret float %r4
 }
 ; CHECK-LABEL: test_sqrt_float
 ; CHECK: sqrtss xmm{{.*}}
 ; CHECK: sqrtss xmm{{.*}}
 ; CHECK: sqrtss xmm{{.*}},DWORD PTR
 ; ARM32-LABEL: test_sqrt_float
 ; ARM32: vsqrt.f32
 ; ARM32: vsqrt.f32
 ; ARM32: vsqrt.f32
 ; ARM32: vadd.f32
+; MIPS32-LABEL: test_sqrt_float
+; MIPS32: sqrt.s
+; MIPS32: sqrt.s
+; MIPS32: sqrt.s
+; MIPS32: add.s
 
 define internal float @test_sqrt_float_mergeable_load(float %x, i32 %iptr) {
 entry:
   %__2 = inttoptr i32 %iptr to float*
   %y = load float, float* %__2, align 4
   %r5 = call float @llvm.sqrt.f32(float %y)
   %r6 = fadd float %x, %r5
   ret float %r6
 }
 ; CHECK-LABEL: test_sqrt_float_mergeable_load
@@ skipping 15 matching lines @@
 }
 ; CHECK-LABEL: test_sqrt_double
 ; CHECK: sqrtsd xmm{{.*}}
 ; CHECK: sqrtsd xmm{{.*}}
 ; CHECK: sqrtsd xmm{{.*}},QWORD PTR
 ; ARM32-LABEL: test_sqrt_double
 ; ARM32: vsqrt.f64
 ; ARM32: vsqrt.f64
 ; ARM32: vsqrt.f64
 ; ARM32: vadd.f64
+; MIPS32-LABEL: test_sqrt_double
+; MIPS32: sqrt.d
+; MIPS32: sqrt.d
+; MIPS32: sqrt.d
+; MIPS32: add.d
 
 define internal double @test_sqrt_double_mergeable_load(double %x, i32 %iptr) {
 entry:
   %__2 = inttoptr i32 %iptr to double*
   %y = load double, double* %__2, align 8
   %r5 = call double @llvm.sqrt.f64(double %y)
   %r6 = fadd double %x, %r5
   ret double %r6
 }
 ; CHECK-LABEL: test_sqrt_double_mergeable_load
 ; CHECK: sqrtsd xmm{{.*}}
 ; ARM32-LABEL: test_sqrt_double_mergeable_load
 ; ARM32: vldr d{{.*}}
 ; ARM32: vsqrt.f64
 
 define internal float @test_sqrt_ignored(float %x, double %y) {
 entry:
   %ignored1 = call float @llvm.sqrt.f32(float %x)
   %ignored2 = call double @llvm.sqrt.f64(double %y)
   ret float 0.0
 }
 ; CHECKO2REM-LABEL: test_sqrt_ignored
 ; CHECKO2REM-NOT: sqrtss
 ; CHECKO2REM-NOT: sqrtsd
+; MIPS32-LABEL: test_sqrt_ignored
+; MIPS32: sqrt.s
+; MIPS32: sqrt.d
 
 define internal float @test_fabs_float(float %x) {
 entry:
   %r = call float @llvm.fabs.f32(float %x)
   %r2 = call float @llvm.fabs.f32(float %r)
   %r3 = call float @llvm.fabs.f32(float -0.0)
   %r4 = fadd float %r2, %r3
   ret float %r4
 }
 ;;; Specially check that the pand instruction doesn't try to operate on a 32-bit
 ;;; (f32) memory operand, and instead uses two xmm registers.
 ; CHECK-LABEL: test_fabs_float
 ; CHECK: pcmpeqd
 ; CHECK: psrld
 ; CHECK: pand {{.*}}xmm{{.*}}xmm
 ; CHECK: pcmpeqd
 ; CHECK: psrld
 ; CHECK: pand {{.*}}xmm{{.*}}xmm
 ; CHECK: pcmpeqd
 ; CHECK: psrld
 ; CHECK: pand {{.*}}xmm{{.*}}xmm
+; MIPS32-LABEL: test_fabs_float
+; MIPS32: abs.s
+; MIPS32: abs.s
+; MIPS32: abs.s
+; MIPS32: add.s
 
 define internal double @test_fabs_double(double %x) {
 entry:
   %r = call double @llvm.fabs.f64(double %x)
   %r2 = call double @llvm.fabs.f64(double %r)
   %r3 = call double @llvm.fabs.f64(double -0.0)
   %r4 = fadd double %r2, %r3
   ret double %r4
 }
 ;;; Specially check that the pand instruction doesn't try to operate on a 64-bit
 ;;; (f64) memory operand, and instead uses two xmm registers.
 ; CHECK-LABEL: test_fabs_double
 ; CHECK: pcmpeqd
 ; CHECK: psrlq
 ; CHECK: pand {{.*}}xmm{{.*}}xmm
 ; CHECK: pcmpeqd
 ; CHECK: psrlq
 ; CHECK: pand {{.*}}xmm{{.*}}xmm
 ; CHECK: pcmpeqd
 ; CHECK: psrlq
 ; CHECK: pand {{.*}}xmm{{.*}}xmm
+; MIPS32-LABEL: test_fabs_double
+; MIPS32: abs.d
+; MIPS32: abs.d
+; MIPS32: abs.d
+; MIPS32: add.d
 
 define internal <4 x float> @test_fabs_v4f32(<4 x float> %x) {
 entry:
   %r = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
   %r2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %r)
   %r3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> undef)
   %r4 = fadd <4 x float> %r2, %r3
   ret <4 x float> %r4
 }
 ; CHECK-LABEL: test_fabs_v4f32
@@ skipping 191 matching lines @@
 
 define internal i32 @test_popcount_32(i32 %x) {
 entry:
   %r = call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %r
 }
 ; CHECK-LABEL: test_popcount_32
 ; CHECK: call {{.*}} R_{{.*}} __popcountsi2
 ; ARM32-LABEL: test_popcount_32
 ; ARM32: bl {{.*}} __popcountsi2
+; MIPS32-LABEL: test_popcount_32
+; MIPS32: jal {{.*}} __popcountsi2
 
 define internal i64 @test_popcount_64(i64 %x) {
 entry:
   %r = call i64 @llvm.ctpop.i64(i64 %x)
   ret i64 %r
 }
 ; CHECK-LABEL: test_popcount_64
 ; CHECK: call {{.*}} R_{{.*}} __popcountdi2
 ; __popcountdi2 only returns a 32-bit result, so clear the upper bits of
 ; the return value just in case.
 ; CHECK: mov {{.*}},0x0
 ; ARM32-LABEL: test_popcount_64
 ; ARM32: bl {{.*}} __popcountdi2
 ; ARM32: mov {{.*}}, #0
+; MIPS32-LABEL: test_popcount_64
+; MIPS32: jal {{.*}} __popcountdi2
 
 define internal i32 @test_popcount_64_ret_i32(i64 %x) {
 entry:
   %r_i64 = call i64 @llvm.ctpop.i64(i64 %x)
   %r = trunc i64 %r_i64 to i32
   ret i32 %r
 }
 ; If there is a trunc, then the mov {{.*}}, 0 is dead and gets optimized out.
 ; CHECKO2REM-LABEL: test_popcount_64_ret_i32
 ; CHECKO2REM: call {{.*}} R_{{.*}} __popcountdi2
 ; CHECKO2REM-NOT: mov {{.*}}, 0
+; MIPS32-LABEL: test_popcount_64_ret_i32
+; MIPS32: jal {{.*}} __popcountdi2
+; MIPS32: sw v0,{{.*}}
+; MIPS32: sw v1,{{.*}}
+; MIPS32: lw v0,{{.*}}
+; MIPS32: lw ra,{{.*}}
 
 define internal void @test_stacksave_noalloca() {
 entry:
   %sp = call i8* @llvm.stacksave()
   call void @llvm.stackrestore(i8* %sp)
   ret void
 }
 ; CHECK-LABEL: test_stacksave_noalloca
 ; CHECK: mov {{.*}},esp
 ; CHECK: mov esp,{{.*}}
@@ skipping 37 matching lines @@
 ; CHECK: lea {{.*}},[esp+0x10]
 ; CHECK: lea {{.*}},[esp+0x10]
 ; CHECK: call
 ; CHECK: mov esp,{{.*}}
 ; CHECK: mov esp,ebp
 ; ARM32-LABEL: test_stacksave_multiple
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov sp, {{.*}}