Subzero, MIPS32: Floating point support in ELF output

src/IceAssemblerMIPS32.cpp

 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 84 matching lines @@
   if (BuildDefs::dump() && !getFlags().getDisableHybridAssembly()) {
     constexpr SizeT InstSize = 0;
     emitTextInst(Node->getAsmName() + ":", InstSize);
   }
   SizeT NodeNumber = Node->getIndex();
   assert(!getPreliminary());
   Label *L = getOrCreateCfgNodeLabel(NodeNumber);
   this->bind(L);
 }
 
 // Checks that Offset can fit in imm16 constant of branch instruction.

[Jim Stichnoth, 2016/09/15 04:53:45]

Can all the code from here down to the note below, be put into an anonymous
namespace?

[obucinac, 2016/09/15 13:35:06]

Done.

 void assertCanEncodeBranchOffset(IOffsetT Offset) {
   (void)Offset;
   (void)kBranchOffsetBits;
   assert(Utils::IsAligned(Offset, 4));
   assert(Utils::IsInt(kBranchOffsetBits, Offset >> 2));
 }
 
 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst) {
   Offset -= kPCReadOffset;
   assertCanEncodeBranchOffset(Offset);
@@ skipping 23 matching lines @@
 }
 
 enum RegSetWanted { WantGPRegs, WantFPRegs };
 
 IValueT getEncodedGPRegNum(const Variable *Var) {
   assert(Var->hasReg());
   const auto Reg = Var->getRegNum();
   return RegMIPS32::getEncodedGPR(Reg);
 }
 
+IValueT getEncodedFPRegNum(const Variable *Var) {
+  assert(Var->hasReg());
+  const auto Reg = Var->getRegNum();
+  if (RegMIPS32::isFPRReg(Reg)) {
+    return RegMIPS32::getEncodedFPR(Reg);
+  } else {

[Jim Stichnoth, 2016/09/15 04:53:45]

http://llvm.org/docs/CodingStandards.html#don-t-use-else-after-a-return

[obucinac, 2016/09/15 13:35:06]

Done.

+    return RegMIPS32::getEncodedFPR64(Reg);
+  }
+}
+
 bool encodeOperand(const Operand *Opnd, IValueT &Value,
                    RegSetWanted WantedRegSet) {
   Value = 0;
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       switch (WantedRegSet) {
       case WantGPRegs:
         Value = getEncodedGPRegNum(Var);
         break;
-      default:
+      case WantFPRegs:
+        Value = getEncodedFPRegNum(Var);
         break;
       }
       return true;
     }
     return false;
   }
   return false;
 }
 
 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet,
                        const char *RegName, const char *InstName) {
   IValueT Reg = 0;
   if (encodeOperand(OpReg, Reg, WantedRegSet) != true)
     llvm::report_fatal_error(std::string(InstName) + ": Can't find register " +
                              RegName);
   return Reg;
 }
 
 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName,
                          const char *InstName) {
   return encodeRegister(OpReg, WantGPRegs, RegName, InstName);
 }
 
+IValueT encodeFPRegister(const Operand *OpReg, const char *RegName,
+                         const char *InstName) {
+  return encodeRegister(OpReg, WantFPRegs, RegName, InstName);
+}
+

[Jim Stichnoth, 2016/09/15 04:53:45]

Here's where my proposed anonymous namespace would end.

[obucinac, 2016/09/15 13:35:06]

Done.

 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt,
                                     const Operand *OpRs, const uint32_t Imm,
                                     const char *InsnName) {
   const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName);
   const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
 
   Opcode |= Rs << 21;
   Opcode |= Rt << 16;
   Opcode |= Imm & 0xffff;
 
   emitInst(Opcode);
 }
 
+void AssemblerMIPS32::emitFtRsImm16(IValueT Opcode, const Operand *OpFt,
+                                    const Operand *OpRs, const uint32_t Imm,
+                                    const char *InsnName) {
+  const IValueT Ft = encodeFPRegister(OpFt, "Ft", InsnName);
+  const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
+
+  Opcode |= Rs << 21;
+  Opcode |= Ft << 16;
+  Opcode |= Imm & 0xffff;
+
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::emitRdRtSa(IValueT Opcode, const Operand *OpRd,
                                  const Operand *OpRt, const uint32_t Sa,
                                  const char *InsnName) {
   const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName);
   const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName);
 
   Opcode |= Rt << 16;
   Opcode |= Rd << 11;
   Opcode |= (Sa & 0x1f) << 6;
 
   emitInst(Opcode);
 }
 
 void AssemblerMIPS32::emitRdRsRt(IValueT Opcode, const Operand *OpRd,
                                  const Operand *OpRs, const Operand *OpRt,
                                  const char *InsnName) {
   const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName);
   const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
   const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName);
 
   Opcode |= Rs << 21;
   Opcode |= Rt << 16;
   Opcode |= Rd << 11;
 
   emitInst(Opcode);
 }
 
+void AssemblerMIPS32::emitFPFormatFtFsFd(
+    IValueT Opcode, FPInstDataFormat Format, const Operand *OpFd,
+    const Operand *OpFs, const Operand *OpFt, const char *InsnName) {
+  const IValueT Fd = encodeFPRegister(OpFd, "Fd", InsnName);
+  const IValueT Fs = encodeFPRegister(OpFs, "Fs", InsnName);
+  const IValueT Ft = encodeFPRegister(OpFt, "Ft", InsnName);
+
+  Opcode |= Fd << 6;
+  Opcode |= Fs << 11;
+  Opcode |= Ft << 16;
+  Opcode |= Format << 21;
+
+  emitInst(Opcode);
+}
+
+void AssemblerMIPS32::add_d(const Operand *OpFd, const Operand *OpFs,
+                            const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000000;
+  emitFPFormatFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "add.d");
+}
+
+void AssemblerMIPS32::add_s(const Operand *OpFd, const Operand *OpFs,
+                            const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000000;
+  emitFPFormatFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "add.s");
+}
+
+void AssemblerMIPS32::div_d(const Operand *OpFd, const Operand *OpFs,
+                            const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000003;
+  emitFPFormatFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "div.d");
+}
+
+void AssemblerMIPS32::div_s(const Operand *OpFd, const Operand *OpFs,
+                            const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000003;
+  emitFPFormatFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "div.s");
+}
+
+void AssemblerMIPS32::mul_d(const Operand *OpFd, const Operand *OpFs,
+                            const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000002;
+  emitFPFormatFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "mul.d");
+}
+
+void AssemblerMIPS32::mul_s(const Operand *OpFd, const Operand *OpFs,
+                            const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000002;
+  emitFPFormatFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "mul.s");
+}
+
+void AssemblerMIPS32::sub_d(const Operand *OpFd, const Operand *OpFs,
+                            const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000001;
+  emitFPFormatFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "sub.d");
+}
+
+void AssemblerMIPS32::sub_s(const Operand *OpFd, const Operand *OpFs,
+                            const Operand *OpFt) {
+  static constexpr IValueT Opcode = 0x44000001;
+  emitFPFormatFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "sub.s");
+}
+
 void AssemblerMIPS32::addiu(const Operand *OpRt, const Operand *OpRs,
                             const uint32_t Imm) {
   static constexpr IValueT Opcode = 0x24000000;
   emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "addiu");
 }
 
 void AssemblerMIPS32::slti(const Operand *OpRt, const Operand *OpRs,
                            const uint32_t Imm) {
   static constexpr IValueT Opcode = 0x28000000;
   emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "slti");
@@ skipping 83 matching lines @@
 }
 
 void AssemblerMIPS32::slt(const Operand *OpRd, const Operand *OpRs,
                           const Operand *OpRt) {
   static constexpr IValueT Opcode = 0x0000002A;
   emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "slt");
 }
 
 void AssemblerMIPS32::sw(const Operand *OpRt, const Operand *OpBase,
                          const uint32_t Offset) {
-  static constexpr IValueT Opcode = 0xAC000000;
-  emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sw");
+  switch (OpRt->getType()) {
+  case IceType_i1:
+  case IceType_i8: {
+    static constexpr IValueT Opcode = 0xA0000000;
+    emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sb");
+    break;
+  }
+  case IceType_i16: {
+    static constexpr IValueT Opcode = 0xA4000000;
+    emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sh");
+    break;
+  }
+  case IceType_i32: {
+    static constexpr IValueT Opcode = 0xAC000000;
+    emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sw");
+    break;
+  }
+  case IceType_f32: {
+    static constexpr IValueT Opcode = 0xE4000000;
+    emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "swc1");
+    break;
+  }
+  case IceType_f64: {
+    static constexpr IValueT Opcode = 0xF4000000;
+    emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "sdc1");
+    break;
+  }
+  default: { UnimplementedError(getFlags()); }
+  }
 }
 
 void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase,
                          const uint32_t Offset) {
-  static constexpr IValueT Opcode = 0x8C000000;
-  emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lw");
+  switch (OpRt->getType()) {
+  case IceType_i1:
+  case IceType_i8: {
+    static constexpr IValueT Opcode = 0x80000000;
+    emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lb");
+  }
+  case IceType_i16: {
+    static constexpr IValueT Opcode = 0x84000000;
+    emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lh");
+  }
+  case IceType_i32: {
+    static constexpr IValueT Opcode = 0x8C000000;
+    emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lw");
+    break;
+  }
+  case IceType_f32: {
+    static constexpr IValueT Opcode = 0xC4000000;
+    emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "lwc1");
+  }
+  case IceType_f64: {
+    static constexpr IValueT Opcode = 0xD4000000;
+    emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "ldc1");
+    break;
+  }
+  default: { UnimplementedError(getFlags()); }
+  }
 }
 
 void AssemblerMIPS32::ret(void) {
   static constexpr IValueT Opcode = 0x03E00008; // JR $31
   emitInst(Opcode);
   nop(); // delay slot
 }
 
 void AssemblerMIPS32::emitBr(const CondMIPS32::Cond Cond, const Operand *OpRs,
                              const Operand *OpRt, IOffsetT Offset) {
@@ skipping 77 matching lines @@
     emitBr(Cond, OpRs, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice