Subzero, MIPS32: Floating point support in ELF output

Subzero, MIPS32: Floating point support in ELF output

Patch implements improvements and instruction encodings for many COP1 instructions for handling floating point values.

Patch covers load, store, basic arithmetic, data movement for FPR<->FPR, GPR<->FPR, FPR<->GPR, and format conversion instructinos.

Added instruction encodings:
Load: lb, lh, lwc1, ldc1
Store: sb, sh, swc1, sdc1
FP arith: abs_d, abs_s, add_d, add_s, div_d, div_s, mul_d, mul_s, sqrt_d, sqrt_s, sub_d, sub_s
FP movs: mfc1, mov_d, mov_s, movn_d, movn_s, movz_d, movz_s, mtc1
Conversion: cvt_d_l, cvt_d_s, cvt_d_w, cvt_s_d, cvt_s_l, cvt_s_w, trunc_l_d, trunc_l_s, trunc_w_d, trunc_w_s

R=stichnot@chromium.org

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=132ea7a52c758a05aabec13cb427558a86ab4eda

[obucinac, 2016-09-14 19:11:13]

Description was changed from

==========
Subzero, MIPS32: Encodings for Load, Store and FP arithmetic intructions

Patch implements obj encodings output for missing load and store
and basic floating point arithmetic instructions.

Added instructions:

lb, lh, lwc1, ldc1, sb, sh, swc1, sdc1
add_d, add_s, div_d, div_s, mul_d, mul_s, sub_d, sub_s
==========

to

==========
Subzero, MIPS32: Encodings for Load, Store and FP arithmetic intructions

Patch implements obj encodings output for missing load and store
and basic floating point arithmetic instructions.

Added instructions:

lb, lh, lwc1, ldc1, sb, sh, swc1, sdc1
add_d, add_s, div_d, div_s, mul_d, mul_s, sub_d, sub_s
==========

[obucinac, 2016-09-14 19:11:13]

obucinac@gmail.com changed reviewers:
+ eholk@chromium.org, jaydeep.patil@imgtec.com, jpp@chromium.org,
kschimpf@google.com, sagar.thakur@imgtec.com, stichnot@chromium.org

[obucinac, 2016-09-14 19:15:03]

Before anything else, I need advice on how to create tests for ELF output.

When I run appropriate commands for my test file, I see correct encoding for
everything I added. But, how to create tests?


Commands:

./pnacl-sz --target=mips32 --bitcode-format=llvm --filetype=obj ./test.ll -o
a.out
mipsel-linux-gnu-objdump -Dr a.out


Test file

define internal float @elfAddFloat(float %a, float %b) {
entry:
  %c = fadd float %a, %b
  ret float %c
}

define internal double @elfAddDouble(double %a, double %b) {
entry:
  %c = fadd double %a, %b
  ret double %c
}

define internal float @elfDivFloat(float %a, float %b) {
entry:
  %c = fdiv float %a, %b
  ret float %c
}

define internal double @elfDivDouble(double %a, double %b) {
entry:
  %c = fdiv double %a, %b
  ret double %c
}

define internal float @elfMulFloat(float %a, float %b) {
entry:
  %c = fmul float %a, %b
  ret float %c
}

define internal double @elfMulDouble(double %a, double %b) {
entry:
  %c = fmul double %a, %b
  ret double %c
}

define internal float @elfSubFloat(float %a, float %b) {
entry:
  %c = fsub float %a, %b
  ret float %c
}

define internal double @elfSubDouble(double %a, double %b) {
entry:
  %c = fsub double %a, %b
  ret double %c
}

[Jim Stichnoth, 2016-09-15 04:53:45]

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.cpp
File src/IceAssemblerMIPS32.cpp (right):

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.cpp#...
src/IceAssemblerMIPS32.cpp:105: // Checks that Offset can fit in imm16 constant
of branch instruction.
Can all the code from here down to the note below, be put into an anonymous
namespace?

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.cpp#...
src/IceAssemblerMIPS32.cpp:154: } else {
http://llvm.org/docs/CodingStandards.html#don-t-use-else-after-a-return

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.cpp#...
src/IceAssemblerMIPS32.cpp:197: 
Here's where my proposed anonymous namespace would end.

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.h
File src/IceAssemblerMIPS32.h (right):

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.h#ne...
src/IceAssemblerMIPS32.h:64: const uint32_t Imm, const char *InsnName);
"const uint32_t" is kind of odd as a function argument.  Should all these be
just "uint32_t"?

https://codereview.chromium.org/2341713003/diff/1/src/IceInstMIPS32.h
File src/IceInstMIPS32.h (right):

https://codereview.chromium.org/2341713003/diff/1/src/IceInstMIPS32.h#newcode...
src/IceInstMIPS32.h:1182: template <> void InstMIPS32Add_d::emitIAS(const Cfg
*Func) const;
Thanks for this! :)

(after learning again, the hard way, that g++ on Windows needs this...)

[Jim Stichnoth, 2016-09-15 05:19:10]

On 2016/09/14 19:15:03, obucinac wrote:
> Before anything else, I need advice on how to create tests for ELF output.
> 
> When I run appropriate commands for my test file, I see correct encoding for
> everything I added. But, how to create tests?
> 
> 
> Commands:
> 
> ./pnacl-sz --target=mips32 --bitcode-format=llvm --filetype=obj ./test.ll -o
> a.out
> mipsel-linux-gnu-objdump -Dr a.out
> 
> 
> Test file
> 
> define internal float @elfAddFloat(float %a, float %b) {
> entry:
>   %c = fadd float %a, %b
>   ret float %c
> }
> 
> define internal double @elfAddDouble(double %a, double %b) {
> entry:
>   %c = fadd double %a, %b
>   ret double %c
> }
> 
> define internal float @elfDivFloat(float %a, float %b) {
> entry:
>   %c = fdiv float %a, %b
>   ret float %c
> }
> 
> define internal double @elfDivDouble(double %a, double %b) {
> entry:
>   %c = fdiv double %a, %b
>   ret double %c
> }
> 
> define internal float @elfMulFloat(float %a, float %b) {
> entry:
>   %c = fmul float %a, %b
>   ret float %c
> }
> 
> define internal double @elfMulDouble(double %a, double %b) {
> entry:
>   %c = fmul double %a, %b
>   ret double %c
> }
> 
> define internal float @elfSubFloat(float %a, float %b) {
> entry:
>   %c = fsub float %a, %b
>   ret float %c
> }
> 
> define internal double @elfSubDouble(double %a, double %b) {
> entry:
>   %c = fsub double %a, %b
>   ret double %c
> }

Have you looked at the ARM integrated assembler tests in
tests_lit/assembler/arm32/ ?

In most of these, we used very simple test functions, and relied on -O2 register
allocation, plus arguments and return values being in registers, to avoid loads
and stores.  We would test:

1. filetype=asm output as a reference test, since we know filetype=asm is
already working.

2. filetype=iasm output to test the actual sequence of bytes.

3. Both of the above, sent to the assembler and disassembler (objdump), as
another validation of the actual bytes, and they should both be equal.

The key here is that we did *not* test the ELF emitter, just the integrated
assembler.

I think ELF tests may have been limited to x86, mostly just to test that
sections, symbols, and the like were encoded as expected.  The CL to add ARM32
ELF support was almost a trivial delta.  I expect the same will be true for
MIPS32 ELF support.

The other thing to note is that for ARM, we had the concept of a "hybrid
assembler".  With filetype=iasm, if we didn't have an emitIAS() implementation
for a particular instruction, we could fall back to using emit(), so we get a
mix of ".byte" style output with normal textual asm instructions.  Note that
even though ARM emitIAS() is entirely implemented, the movt/movw instructions
still have to be emitted as "movt" and "movw" in filetype=iasm mode, because
llvm-mc doesn't allow the special movt/movw relocation types to be expressed
without using the actual movt/movw instruction mnemonics.

[obucinac, 2016-09-15 13:22:57]

I added more instruction encodings in order to make tests runable.

[obucinac, 2016-09-15 13:34:09]

Description was changed from

==========
Subzero, MIPS32: Encodings for Load, Store and FP arithmetic intructions

Patch implements obj encodings output for missing load and store
and basic floating point arithmetic instructions.

Added instructions:

lb, lh, lwc1, ldc1, sb, sh, swc1, sdc1
add_d, add_s, div_d, div_s, mul_d, mul_s, sub_d, sub_s
==========

to

==========
Subzero, MIPS32: Floating point support in ELF output

Patch implements improvements and instruction encodings for many COP1
instructions for handling floating point values.

Patch covers load, store, basic arithmetic and data movement for FPR<->FPR,
GPR<->FPR, FPR<->GPR.

Added instruction encodings: 
Load: lb, lh, lwc1, ldc1
Store: sb, sh, swc1, sdc1
FP arith: abs_d, abs_s, add_d, add_s, div_d, div_s, mul_d, mul_s, sqrt_d,
sqrt_s, sub_d, sub_s
FP movs: mfc1, mov_d, mov_s, movn_d, movn_s, movz_d, movz_s, mtc1
==========

[obucinac, 2016-09-15 13:34:59]

On 2016/09/15 13:22:57, obucinac wrote:
> I added more instruction encodings in order to make tests runable.

I also changed commit message, to better reflect patch content.

[obucinac, 2016-09-15 13:35:06]

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.cpp
File src/IceAssemblerMIPS32.cpp (right):

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.cpp#...
src/IceAssemblerMIPS32.cpp:105: // Checks that Offset can fit in imm16 constant
of branch instruction.
On 2016/09/15 04:53:45, stichnot wrote:
> Can all the code from here down to the note below, be put into an anonymous
> namespace?

Done.

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.cpp#...
src/IceAssemblerMIPS32.cpp:154: } else {
On 2016/09/15 04:53:45, stichnot wrote:
> http://llvm.org/docs/CodingStandards.html#don-t-use-else-after-a-return

Done.

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.cpp#...
src/IceAssemblerMIPS32.cpp:197: 
On 2016/09/15 04:53:45, stichnot wrote:
> Here's where my proposed anonymous namespace would end.

Done.

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.h
File src/IceAssemblerMIPS32.h (right):

https://codereview.chromium.org/2341713003/diff/1/src/IceAssemblerMIPS32.h#ne...
src/IceAssemblerMIPS32.h:64: const uint32_t Imm, const char *InsnName);
On 2016/09/15 04:53:45, stichnot wrote:
> "const uint32_t" is kind of odd as a function argument.  Should all these be
> just "uint32_t"?

I dont have the opinion on this, I was just following the convention I found in
the file.

Removed.

https://codereview.chromium.org/2341713003/diff/1/src/IceInstMIPS32.h
File src/IceInstMIPS32.h (right):

https://codereview.chromium.org/2341713003/diff/1/src/IceInstMIPS32.h#newcode...
src/IceInstMIPS32.h:1182: template <> void InstMIPS32Add_d::emitIAS(const Cfg
*Func) const;
On 2016/09/15 04:53:45, stichnot wrote:
> Thanks for this! :)
> 
> (after learning again, the hard way, that g++ on Windows needs this...)

Acknowledged.

[jaydeep.patil, 2016-09-16 03:23:02]

On 2016/09/15 13:34:59, obucinac wrote:
> On 2016/09/15 13:22:57, obucinac wrote:
> > I added more instruction encodings in order to make tests runable.
> 
> I also changed commit message, to better reflect patch content.

We already have tests for ELF output. 
Please refer to tests_lit/assembler/mips32 for tests. 
Following functions would generate additional 45 instructions to test:  

declare float @llvm.sqrt.f32(float)
declare double @llvm.sqrt.f64(double)
declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double)

define internal float @test_03(float %x) {
entry:
  %r1 = call float @llvm.sqrt.f32(float %x)
  %r2 = call float @llvm.fabs.f32(float %x)
  %r3 = fadd float %r1, %r2
  %r4 = fsub float %r3, %r1
  %r5 = fdiv float %r4, %r2
  %r6 = fmul float %r4, %r5
  ret float %r6
}

define internal double @test_04(double %x) {
entry:
  %r1 = call double @llvm.sqrt.f64(double %x)
  %r2 = call double @llvm.fabs.f64(double %x)
  %r3 = fadd double %r1, %r2
  %r4 = fsub double %r3, %r1
  %r5 = fdiv double %r4, %r2
  %r6 = fmul double %r4, %r5
  ret double %r6
}

define internal i32 @test_05(float %a, float %b) {
entry:
  %cmp1 = fcmp oeq float %a, %b
  br i1 %cmp1, label %if.then1, label %if.return1

if.then1:
  %cmp2 = fcmp ogt float %a, %b
  br i1 %cmp2, label %if.then2, label %if.return1

if.then2:
  %cmp4 = fcmp ult float %a, %b
  br i1 %cmp4, label %if.then3, label %if.return1

if.then3:
  %cmp5 = fcmp olt float %a, %b
  br i1 %cmp5, label %if.then4, label %if.return1

if.then4:
  %cmp6 = fcmp ugt float %a, %b
  br i1 %cmp6, label %if.then5, label %if.return1

if.then5:
  %cmp7 = fcmp ule float %a, %b
  br i1 %cmp6, label %if.then6, label %if.return1
 
if.then6:
  %cmp8 = fcmp ord float %a, %b
  br i1 %cmp8, label %if.then7, label %if.return1

if.then7:
  %cmp9 = fcmp ueq float %a, %b
  br i1 %cmp9, label %if.then8, label %if.return1

if.then8:
  %cmp3 = fcmp uno float %a, %b
  br i1 %cmp3, label %if.then9, label %if.return1

if.then9:
  br label %if.return2

if.return1:
  ret i32 1

if.return2:
  ret i32 2
}

define internal i32 @test_06(double %a, double %b) {
entry:
  %cmp1 = fcmp oeq double %a, %b
  br i1 %cmp1, label %if.then1, label %if.return1

if.then1:
  %cmp2 = fcmp ogt double %a, %b
  br i1 %cmp2, label %if.then2, label %if.return1

if.then2:
  %cmp4 = fcmp ult double %a, %b
  br i1 %cmp4, label %if.then3, label %if.return1

if.then3:
  %cmp5 = fcmp olt double %a, %b
  br i1 %cmp5, label %if.then4, label %if.return1

if.then4:
  %cmp6 = fcmp ugt double %a, %b
  br i1 %cmp6, label %if.then5, label %if.return1

if.then5:
  %cmp7 = fcmp ule double %a, %b
  br i1 %cmp6, label %if.then6, label %if.return1
 
if.then6:
  %cmp8 = fcmp ord double %a, %b
  br i1 %cmp8, label %if.then7, label %if.return1

if.then7:
  %cmp9 = fcmp ueq double %a, %b
  br i1 %cmp9, label %if.then8, label %if.return1

if.then8:
  %cmp3 = fcmp uno double %a, %b
  br i1 %cmp3, label %if.then9, label %if.return1

if.then9:
  br label %if.return2

if.return1:
  ret i32 1

if.return2:
  ret i32 2
}

define internal float @signed32ToFloat(i32 %a) {
entry:
  %conv = sitofp i32 %a to float
  ret float %conv
}

define internal double @fpext(float %a) {
entry:
  %conv = fpext float %a to double
  ret double %conv
}

define internal i32 @floatToSigned32(float %a) {
entry:
  %conv = fptosi float %a to i32
  ret i32 %conv
}

define internal i64 @mul64BitSigned(i64 %a, i64 %b) {
entry:
  %mul = mul i64 %b, %a
  ret i64 %mul
}

define internal i32 @shlImmLarge(i32 %val) {
entry:
  %r1 = shl i32 %val, 2
  %r2 = lshr i32 %val, 2
  %r3 = ashr i32 %val, 2
  %r4 = add i32 %r1, %r2
  %r5 = add i32 %r4, %r3
  ret i32 %r5
}

[Jim Stichnoth, 2016-09-16 03:25:01]

https://codereview.chromium.org/2341713003/diff/20001/src/IceAssemblerMIPS32.cpp
File src/IceAssemblerMIPS32.cpp (right):

https://codereview.chromium.org/2341713003/diff/20001/src/IceAssemblerMIPS32....
src/IceAssemblerMIPS32.cpp:181: }
// end of anonymous namespace

https://codereview.chromium.org/2341713003/diff/20001/tests_lit/assembler/mip...
File tests_lit/assembler/mips32/encoding_test_arith_fp.ll (right):

https://codereview.chromium.org/2341713003/diff/20001/tests_lit/assembler/mip...
tests_lit/assembler/mips32/encoding_test_arith_fp.ll:46: ; DIS-NEXT:    
c:	00000000 	nop
I'm curious about these nop instructions.

Before each function, the filetype=asm output includes:

        .text
        .p2alignl 4,0x00034

where that 0x34 value comes from:

static constexpr uint8_t TrapBytesRaw[] = {0x00, 0x00, 0x00, 0x34};

So I would have expected that to be the padding, not a nop instruction.

Any ideas?

[jaydeep.patil, 2016-09-16 03:29:42]

On 2016/09/16 03:25:01, stichnot wrote:
>
https://codereview.chromium.org/2341713003/diff/20001/src/IceAssemblerMIPS32.cpp
> File src/IceAssemblerMIPS32.cpp (right):
> 
>
https://codereview.chromium.org/2341713003/diff/20001/src/IceAssemblerMIPS32....
> src/IceAssemblerMIPS32.cpp:181: }
> // end of anonymous namespace
> 
>
https://codereview.chromium.org/2341713003/diff/20001/tests_lit/assembler/mip...
> File tests_lit/assembler/mips32/encoding_test_arith_fp.ll (right):
> 
>
https://codereview.chromium.org/2341713003/diff/20001/tests_lit/assembler/mip...
> tests_lit/assembler/mips32/encoding_test_arith_fp.ll:46: ; DIS-NEXT:    
> c:	00000000 	nop
> I'm curious about these nop instructions.
> 
> Before each function, the filetype=asm output includes:
> 
>         .text
>         .p2alignl 4,0x00034
> 
> where that 0x34 value comes from:
> 
> static constexpr uint8_t TrapBytesRaw[] = {0x00, 0x00, 0x00, 0x34};
> 
> So I would have expected that to be the padding, not a nop instruction.
> 
> Any ideas?

This NOP is generated by the assembler to fill the delay slot.
As the generated assembly code is not in ".set noreorder" block, assembler fills
the delay slot with a NOP. It inserts a NOP after every branch/jump/call
instruction.

[obucinac, 2016-09-16 17:47:50]

Description was changed from

==========
Subzero, MIPS32: Floating point support in ELF output

Patch implements improvements and instruction encodings for many COP1
instructions for handling floating point values.

Patch covers load, store, basic arithmetic and data movement for FPR<->FPR,
GPR<->FPR, FPR<->GPR.

Added instruction encodings: 
Load: lb, lh, lwc1, ldc1
Store: sb, sh, swc1, sdc1
FP arith: abs_d, abs_s, add_d, add_s, div_d, div_s, mul_d, mul_s, sqrt_d,
sqrt_s, sub_d, sub_s
FP movs: mfc1, mov_d, mov_s, movn_d, movn_s, movz_d, movz_s, mtc1
==========

to

==========
Subzero, MIPS32: Floating point support in ELF output

Patch implements improvements and instruction encodings for many COP1
instructions for handling floating point values.

Patch covers load, store, basic arithmetic and data movement for FPR<->FPR,
GPR<->FPR, FPR<->GPR.

Added instruction encodings: 
Load: lb, lh, lwc1, ldc1
Store: sb, sh, swc1, sdc1
FP arith: abs_d, abs_s, add_d, add_s, div_d, div_s, mul_d, mul_s, sqrt_d,
sqrt_s, sub_d, sub_s
FP movs: mfc1, mov_d, mov_s, movn_d, movn_s, movz_d, movz_s, mtc1
Conversion: cvt_d_l, cvt_d_s, cvt_d_w, cvt_s_d, cvt_s_l, cvt_s_w, trunc_l_d,
trunc_l_s, trunc_w_d, trunc_w_s
==========

[obucinac, 2016-09-16 17:48:23]

Description was changed from

==========
Subzero, MIPS32: Floating point support in ELF output

Patch implements improvements and instruction encodings for many COP1
instructions for handling floating point values.

Patch covers load, store, basic arithmetic and data movement for FPR<->FPR,
GPR<->FPR, FPR<->GPR.

Added instruction encodings: 
Load: lb, lh, lwc1, ldc1
Store: sb, sh, swc1, sdc1
FP arith: abs_d, abs_s, add_d, add_s, div_d, div_s, mul_d, mul_s, sqrt_d,
sqrt_s, sub_d, sub_s
FP movs: mfc1, mov_d, mov_s, movn_d, movn_s, movz_d, movz_s, mtc1
Conversion: cvt_d_l, cvt_d_s, cvt_d_w, cvt_s_d, cvt_s_l, cvt_s_w, trunc_l_d,
trunc_l_s, trunc_w_d, trunc_w_s
==========

to

==========
Subzero, MIPS32: Floating point support in ELF output

Patch implements improvements and instruction encodings for many COP1
instructions for handling floating point values.

Patch covers load, store, basic arithmetic, data movement for FPR<->FPR,
GPR<->FPR, FPR<->GPR, and format conversion instructinos.

Added instruction encodings: 
Load: lb, lh, lwc1, ldc1
Store: sb, sh, swc1, sdc1
FP arith: abs_d, abs_s, add_d, add_s, div_d, div_s, mul_d, mul_s, sqrt_d,
sqrt_s, sub_d, sub_s
FP movs: mfc1, mov_d, mov_s, movn_d, movn_s, movz_d, movz_s, mtc1
Conversion: cvt_d_l, cvt_d_s, cvt_d_w, cvt_s_d, cvt_s_l, cvt_s_w, trunc_l_d,
trunc_l_s, trunc_w_d, trunc_w_s
==========

[Jim Stichnoth, 2016-09-18 14:30:07]

On 2016/09/16 03:29:42, jaydeep.patil wrote:
> On 2016/09/16 03:25:01, stichnot wrote:
> >
>
https://codereview.chromium.org/2341713003/diff/20001/src/IceAssemblerMIPS32.cpp
> > File src/IceAssemblerMIPS32.cpp (right):
> > 
> >
>
https://codereview.chromium.org/2341713003/diff/20001/src/IceAssemblerMIPS32....
> > src/IceAssemblerMIPS32.cpp:181: }
> > // end of anonymous namespace
> > 
> >
>
https://codereview.chromium.org/2341713003/diff/20001/tests_lit/assembler/mip...
> > File tests_lit/assembler/mips32/encoding_test_arith_fp.ll (right):
> > 
> >
>
https://codereview.chromium.org/2341713003/diff/20001/tests_lit/assembler/mip...
> > tests_lit/assembler/mips32/encoding_test_arith_fp.ll:46: ; DIS-NEXT:    
> > c:	00000000 	nop
> > I'm curious about these nop instructions.
> > 
> > Before each function, the filetype=asm output includes:
> > 
> >         .text
> >         .p2alignl 4,0x00034
> > 
> > where that 0x34 value comes from:
> > 
> > static constexpr uint8_t TrapBytesRaw[] = {0x00, 0x00, 0x00, 0x34};
> > 
> > So I would have expected that to be the padding, not a nop instruction.
> > 
> > Any ideas?
> 
> This NOP is generated by the assembler to fill the delay slot.
> As the generated assembly code is not in ".set noreorder" block, assembler
fills
> the delay slot with a NOP. It inserts a NOP after every branch/jump/call
> instruction.

Ah, thanks.

LGTM.

(I went ahead and made the "anonymous namespace" comment change.)

[Jim Stichnoth, 2016-09-18 14:30:21]

Description was changed from

==========
Subzero, MIPS32: Floating point support in ELF output

Patch implements improvements and instruction encodings for many COP1
instructions for handling floating point values.

Patch covers load, store, basic arithmetic, data movement for FPR<->FPR,
GPR<->FPR, FPR<->GPR, and format conversion instructinos.

Added instruction encodings: 
Load: lb, lh, lwc1, ldc1
Store: sb, sh, swc1, sdc1
FP arith: abs_d, abs_s, add_d, add_s, div_d, div_s, mul_d, mul_s, sqrt_d,
sqrt_s, sub_d, sub_s
FP movs: mfc1, mov_d, mov_s, movn_d, movn_s, movz_d, movz_s, mtc1
Conversion: cvt_d_l, cvt_d_s, cvt_d_w, cvt_s_d, cvt_s_l, cvt_s_w, trunc_l_d,
trunc_l_s, trunc_w_d, trunc_w_s
==========

to

==========
Subzero, MIPS32: Floating point support in ELF output

Patch implements improvements and instruction encodings for many COP1
instructions for handling floating point values.

Patch covers load, store, basic arithmetic, data movement for FPR<->FPR,
GPR<->FPR, FPR<->GPR, and format conversion instructinos.

Added instruction encodings:
Load: lb, lh, lwc1, ldc1
Store: sb, sh, swc1, sdc1
FP arith: abs_d, abs_s, add_d, add_s, div_d, div_s, mul_d, mul_s, sqrt_d,
sqrt_s, sub_d, sub_s
FP movs: mfc1, mov_d, mov_s, movn_d, movn_s, movz_d, movz_s, mtc1
Conversion: cvt_d_l, cvt_d_s, cvt_d_w, cvt_s_d, cvt_s_l, cvt_s_w, trunc_l_d,
trunc_l_s, trunc_w_d, trunc_w_s

R=stichnot@chromium.org

Committed:
https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a...
==========

[Jim Stichnoth, 2016-09-18 14:30:23]

Committed patchset #3 (id:40001) manually as
132ea7a52c758a05aabec13cb427558a86ab4eda (presubmit successful).