Index: test/unittests/compiler/mips/instruction-selector-mips-unittest.cc |
diff --git a/test/unittests/compiler/mips/instruction-selector-mips-unittest.cc b/test/unittests/compiler/mips/instruction-selector-mips-unittest.cc |
index 7b5c667261551f05f31b917a2ebffef68d28ec09..8bbcfb4fb2e88222f95eb772946a88f47d6da036 100644 |
--- a/test/unittests/compiler/mips/instruction-selector-mips-unittest.cc |
+++ b/test/unittests/compiler/mips/instruction-selector-mips-unittest.cc |
@@ -1149,6 +1149,203 @@ TEST_F(InstructionSelectorTest, Float64Abs) { |
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
} |
+TEST_F(InstructionSelectorTest, Float32AddWithFloat32Mul) { |
+ { |
+ StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(), |
+ MachineType::Float32(), MachineType::Float32()); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const p2 = m.Parameter(2); |
+ Node* const n = m.Float32Add(m.Float32Mul(p0, p1), p2); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ ASSERT_EQ(1U, s.size()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_EQ(kMipsMaddS, s[0]->arch_opcode()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_EQ(kMipsMaddfS, s[0]->arch_opcode()); |
+ } |
+ ASSERT_EQ(3U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_FALSE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_TRUE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ EXPECT_EQ(kFlags_none, s[0]->flags_mode()); |
+ } |
+ { |
+ StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(), |
+ MachineType::Float32(), MachineType::Float32()); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const p2 = m.Parameter(2); |
+ Node* const n = m.Float32Add(p0, m.Float32Mul(p1, p2)); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ ASSERT_EQ(1U, s.size()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_EQ(kMipsMaddS, s[0]->arch_opcode()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_EQ(kMipsMaddfS, s[0]->arch_opcode()); |
+ } |
+ ASSERT_EQ(3U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_FALSE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_TRUE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ EXPECT_EQ(kFlags_none, s[0]->flags_mode()); |
+ } |
+} |
+ |
+TEST_F(InstructionSelectorTest, Float64AddWithFloat64Mul) { |
+ { |
+ StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(), |
+ MachineType::Float64(), MachineType::Float64()); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const p2 = m.Parameter(2); |
+ Node* const n = m.Float64Add(m.Float64Mul(p0, p1), p2); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ ASSERT_EQ(1U, s.size()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_EQ(kMipsMaddD, s[0]->arch_opcode()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_EQ(kMipsMaddfD, s[0]->arch_opcode()); |
+ } |
+ ASSERT_EQ(3U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_FALSE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_TRUE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ EXPECT_EQ(kFlags_none, s[0]->flags_mode()); |
+ } |
+ { |
+ StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(), |
+ MachineType::Float64(), MachineType::Float64()); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const p2 = m.Parameter(2); |
+ Node* const n = m.Float64Add(p0, m.Float64Mul(p1, p2)); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ ASSERT_EQ(1U, s.size()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_EQ(kMipsMaddD, s[0]->arch_opcode()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_EQ(kMipsMaddfD, s[0]->arch_opcode()); |
+ } |
+ ASSERT_EQ(3U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_FALSE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_TRUE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ EXPECT_EQ(kFlags_none, s[0]->flags_mode()); |
+ } |
+} |
+ |
+TEST_F(InstructionSelectorTest, Float32SubWithFloat32Mul) { |
+ StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(), |
+ MachineType::Float32(), MachineType::Float32()); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const p2 = m.Parameter(2); |
+ Node* n; |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ n = m.Float32Sub(m.Float32Mul(p1, p2), p0); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ n = m.Float32Sub(p0, m.Float32Mul(p1, p2)); |
+ } |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ ASSERT_EQ(1U, s.size()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_EQ(kMipsMsubS, s[0]->arch_opcode()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_EQ(kMipsMsubfS, s[0]->arch_opcode()); |
+ } |
+ ASSERT_EQ(3U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_FALSE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_TRUE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ EXPECT_EQ(kFlags_none, s[0]->flags_mode()); |
+} |
+ |
+TEST_F(InstructionSelectorTest, Float64SubWithFloat64Mul) { |
+ StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(), |
+ MachineType::Float64(), MachineType::Float64()); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const p2 = m.Parameter(2); |
+ Node* n; |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ n = m.Float64Sub(m.Float64Mul(p1, p2), p0); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ n = m.Float64Sub(p0, m.Float64Mul(p1, p2)); |
+ } |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ ASSERT_EQ(1U, s.size()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_EQ(kMipsMsubD, s[0]->arch_opcode()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_EQ(kMipsMsubfD, s[0]->arch_opcode()); |
+ } |
+ ASSERT_EQ(3U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ if (IsMipsArchVariant(kMips32r2)) { |
+ EXPECT_FALSE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } else if (IsMipsArchVariant(kMips32r6)) { |
+ EXPECT_TRUE( |
+ UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); |
+ } |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ EXPECT_EQ(kFlags_none, s[0]->flags_mode()); |
+} |
TEST_F(InstructionSelectorTest, Float64Max) { |
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(), |