Index: src/compiler/mips64/code-generator-mips64.cc |
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc |
index 7a964801bbe03eff3d0dffa53b815784754beb16..31f6f456ad5f67e816d1aaf210cc61400cd203b1 100644 |
--- a/src/compiler/mips64/code-generator-mips64.cc |
+++ b/src/compiler/mips64/code-generator-mips64.cc |
@@ -1314,6 +1314,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( |
__ sub_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), |
i.InputDoubleRegister(1)); |
break; |
+ case kMips64MaddS: |
+ __ madd_s(i.OutputFloatRegister(), i.InputFloatRegister(0), |
+ i.InputFloatRegister(1), i.InputFloatRegister(2)); |
+ break; |
+ case kMips64MaddD: |
+ __ madd_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), |
+ i.InputDoubleRegister(1), i.InputDoubleRegister(2)); |
+ break; |
+ case kMips64MaddfS: |
+ __ maddf_s(i.OutputFloatRegister(), i.InputFloatRegister(1), |
+ i.InputFloatRegister(2)); |
+ break; |
+ case kMips64MaddfD: |
+ __ maddf_d(i.OutputDoubleRegister(), i.InputDoubleRegister(1), |
+ i.InputDoubleRegister(2)); |
+ break; |
+ case kMips64MsubS: |
+ __ msub_s(i.OutputFloatRegister(), i.InputFloatRegister(0), |
+ i.InputFloatRegister(1), i.InputFloatRegister(2)); |
+ break; |
+ case kMips64MsubD: |
+ __ msub_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), |
+ i.InputDoubleRegister(1), i.InputDoubleRegister(2)); |
+ break; |
+ case kMips64MsubfS: |
+ __ msubf_s(i.OutputFloatRegister(), i.InputFloatRegister(1), |
+ i.InputFloatRegister(2)); |
+ break; |
+ case kMips64MsubfD: |
+ __ msubf_d(i.OutputDoubleRegister(), i.InputDoubleRegister(1), |
+ i.InputDoubleRegister(2)); |
+ break; |
case kMips64MulD: |
// TODO(plind): add special case: right op is -1.0, see arm port. |
__ mul_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), |