Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(602)

Issues Search
    My Issues | Starred     Open | Closed | All

Unified Diff: tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll

Issue 2340733003: Subzero, MIPS32: Randomly insert NOP (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 3 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« pydir/run-pnacl-sz.py ('K') | « src/IceTargetLoweringMIPS32.cpp ('k') | no next file » | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll
diff --git a/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll b/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll
new file mode 100644
index 0000000000000000000000000000000000000000..c025417e5d82d3da10276d2d7da55337e8cd8704
--- /dev/null
+++ b/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll
@@ -0,0 +1,206 @@
+; RUN: %p2i -i %s --filetype=asm --assemble --disassemble --target=mips32 \
+; RUN: -a -skip-unimplemented -sz-seed=1 -nop-insertion \
+; RUN: -nop-insertion-percentage=50 -max-nops-per-instruction=1 \
+; RUN: | FileCheck %s --check-prefix=MIPS32P50N1
+; RUN: %p2i -i %s --filetype=asm --assemble --disassemble --target=mips32 \
+; RUN: -a -skip-unimplemented -sz-seed=1 -nop-insertion \
+; RUN: -nop-insertion-percentage=110 -max-nops-per-instruction=2 \
+; RUN: | FileCheck %s --check-prefix=MIPS32P110N2
+
+
+define internal i32 @nopInsertion(i32 %a, i32 %b, i32 %c) {
+entry:
+ %a1 = add i32 %a, 1
+ %b1 = add i32 %b, 2
+ %c1 = add i32 %c, 3
+ %a2 = sub i32 %a1, 1
+ %b2 = sub i32 %b1, 2
+ %c2 = sub i32 %c1, 3
+ %a3 = mul i32 %a2, %b2
+ %b3 = mul i32 %a3, %c2
+ ret i32 %b3
+}
+
+; MIPS32P50N1-LABEL: nopInsertion
+; MIPS32P50N1: nop
+; MIPS32P50N1: addiu {{.*}}
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: addu {{.*}}
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: addu {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: addu {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: subu {{.*}}
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: subu {{.*}}
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: subu {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: mul {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: mul {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: addiu {{.*}}
+; MIPS32P50N1: jr ra
+; MIPS32P50N1: nop
+
+; MIPS32P110N2-LABEL: nopInsertion
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addiu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: subu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: subu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: subu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: mul {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: mul {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addiu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: jr ra
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
« pydir/run-pnacl-sz.py ('K') | « src/IceTargetLoweringMIPS32.cpp ('k') | no next file » | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698