Subzero, MIPS32: lowerSelect for i1, i8, i16, i32, f32, f64

src/IceInstMIPS32.cpp

 //===- subzero/src/IceInstMips32.cpp - Mips32 instruction implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
@@ skipping 86 matching lines @@
 template <> const char *InstMIPS32Ldc1::Opcode = "ldc1";
 template <> const char *InstMIPS32Lui::Opcode = "lui";
 template <> const char *InstMIPS32Lw::Opcode = "lw";
 template <> const char *InstMIPS32Lwc1::Opcode = "lwc1";
 template <> const char *InstMIPS32Mfc1::Opcode = "mfc1";
 template <> const char *InstMIPS32Mfhi::Opcode = "mfhi";
 template <> const char *InstMIPS32Mflo::Opcode = "mflo";
 template <> const char *InstMIPS32Mov_d::Opcode = "mov.d";
 template <> const char *InstMIPS32Mov_s::Opcode = "mov.s";
 template <> const char *InstMIPS32Movf::Opcode = "movf";
+template <> const char *InstMIPS32Movn::Opcode = "movn";
+template <> const char *InstMIPS32Movn_d::Opcode = "movn.d";
+template <> const char *InstMIPS32Movn_s::Opcode = "movn.s";
 template <> const char *InstMIPS32Movt::Opcode = "movt";
+template <> const char *InstMIPS32Movz::Opcode = "movz";
+template <> const char *InstMIPS32Movz_d::Opcode = "movz.d";
+template <> const char *InstMIPS32Movz_s::Opcode = "movz.s";
 template <> const char *InstMIPS32Mtc1::Opcode = "mtc1";
 template <> const char *InstMIPS32Mthi::Opcode = "mthi";
 template <> const char *InstMIPS32Mtlo::Opcode = "mtlo";
 template <> const char *InstMIPS32Mul::Opcode = "mul";
 template <> const char *InstMIPS32Mul_d::Opcode = "mul.d";
 template <> const char *InstMIPS32Mul_s::Opcode = "mul.s";
 template <> const char *InstMIPS32Mult::Opcode = "mult";
 template <> const char *InstMIPS32Multu::Opcode = "multu";
 template <> const char *InstMIPS32Or::Opcode = "or";
 template <> const char *InstMIPS32Ori::Opcode = "ori";
@@ skipping 612 matching lines @@
   const char *ActualOpcode = nullptr;
   const bool DestIsReg = Dest->hasReg();
   const bool SrcIsReg = (SrcV && SrcV->hasReg());
 
   // reg to reg
   if (DestIsReg && SrcIsReg) {
     const Type DstType = Dest->getType();
     const Type SrcType = Src->getType();
 
     // move GP to/from FP
-    if (DstType != SrcType) {
+    if ((isScalarIntegerType(DstType) && isScalarFloatingType(SrcType)) ||
+        (isScalarFloatingType(DstType) && isScalarIntegerType(SrcType))) {

[obucinac, 2016/09/14 12:39:02]

e.g. IceType_i8 != IceType_i32, triggered emmiting mfc1/mtc1 instructions,
causing invalid operand error.

       if (isScalarFloatingType(DstType)) {
         Str << "\t"
                "mtc1"
                "\t";
         getSrc(0)->emit(Func);
         Str << ", ";
         getDest()->emit(Func);
         return;
       }
       ActualOpcode = "mfc1";
@@ skipping 114 matching lines @@
 template <> void InstMIPS32Lw::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
   auto *Mem = llvm::dyn_cast<OperandMIPS32Mem>(getSrc(0));
   ConstantInteger32 *Offset = llvm::cast<ConstantInteger32>(Mem->getOffset());
   uint32_t Imm = static_cast<uint32_t>(Offset->getValue());
   Asm->lw(getDest(), Mem->getBase(), Imm);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice