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Side by Side Diff: src/IceInstMIPS32.h

Issue 2337023003: Subzero, MIPS32: lowerSelect for i1, i8, i16, i32, f32, f64 (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 3 months ago
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1 //===- subzero/src/IceInstMIPS32.h - MIPS32 machine instrs --*- C++ -*-----===// 1 //===- subzero/src/IceInstMIPS32.h - MIPS32 machine instrs --*- C++ -*-----===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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171 Ldc1, 171 Ldc1,
172 Lui, 172 Lui,
173 Lw, 173 Lw,
174 Lwc1, 174 Lwc1,
175 Mfc1, 175 Mfc1,
176 Mfhi, 176 Mfhi,
177 Mflo, 177 Mflo,
178 Mov, // actually a pseudo op for addi rd, rs, 0 178 Mov, // actually a pseudo op for addi rd, rs, 0
179 Mov_d, 179 Mov_d,
180 Mov_s, 180 Mov_s,
181 Movn,
182 Movn_d,
183 Movn_s,
184 Movz,
185 Movz_d,
186 Movz_s,
181 Mtc1, 187 Mtc1,
182 Mthi, 188 Mthi,
183 Mtlo, 189 Mtlo,
184 Mul, 190 Mul,
185 Mul_d, 191 Mul_d,
186 Mul_s, 192 Mul_s,
187 Mult, 193 Mult,
188 Multu, 194 Multu,
189 Or, 195 Or,
190 Ori, 196 Ori,
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899 using InstMIPS32La = InstMIPS32UnaryopGPR<InstMIPS32::La>; 905 using InstMIPS32La = InstMIPS32UnaryopGPR<InstMIPS32::La>;
900 using InstMIPS32Ldc1 = InstMIPS32Load<InstMIPS32::Ldc1>; 906 using InstMIPS32Ldc1 = InstMIPS32Load<InstMIPS32::Ldc1>;
901 using InstMIPS32Lui = InstMIPS32UnaryopGPR<InstMIPS32::Lui>; 907 using InstMIPS32Lui = InstMIPS32UnaryopGPR<InstMIPS32::Lui>;
902 using InstMIPS32Lw = InstMIPS32Load<InstMIPS32::Lw>; 908 using InstMIPS32Lw = InstMIPS32Load<InstMIPS32::Lw>;
903 using InstMIPS32Lwc1 = InstMIPS32Load<InstMIPS32::Lwc1>; 909 using InstMIPS32Lwc1 = InstMIPS32Load<InstMIPS32::Lwc1>;
904 using InstMIPS32Mfc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mfc1>; 910 using InstMIPS32Mfc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mfc1>;
905 using InstMIPS32Mfhi = InstMIPS32UnaryopGPR<InstMIPS32::Mfhi>; 911 using InstMIPS32Mfhi = InstMIPS32UnaryopGPR<InstMIPS32::Mfhi>;
906 using InstMIPS32Mflo = InstMIPS32UnaryopGPR<InstMIPS32::Mflo>; 912 using InstMIPS32Mflo = InstMIPS32UnaryopGPR<InstMIPS32::Mflo>;
907 using InstMIPS32Mov_d = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_d>; 913 using InstMIPS32Mov_d = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_d>;
908 using InstMIPS32Mov_s = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_s>; 914 using InstMIPS32Mov_s = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_s>;
915 using InstMIPS32Movn = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn>;
916 using InstMIPS32Movn_d = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn_d>;
917 using InstMIPS32Movn_s = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn_s>;
918 using InstMIPS32Movz = InstMIPS32ThreeAddrGPR<InstMIPS32::Movz>;
919 using InstMIPS32Movz_d = InstMIPS32ThreeAddrGPR<InstMIPS32::Movz_d>;
920 using InstMIPS32Movz_s = InstMIPS32ThreeAddrGPR<InstMIPS32::Movz_s>;
909 using InstMIPS32Mtc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mtc1>; 921 using InstMIPS32Mtc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mtc1>;
910 using InstMIPS32Mthi = InstMIPS32UnaryopGPR<InstMIPS32::Mthi>; 922 using InstMIPS32Mthi = InstMIPS32UnaryopGPR<InstMIPS32::Mthi>;
911 using InstMIPS32Mtlo = InstMIPS32UnaryopGPR<InstMIPS32::Mtlo>; 923 using InstMIPS32Mtlo = InstMIPS32UnaryopGPR<InstMIPS32::Mtlo>;
912 using InstMIPS32Mul = InstMIPS32ThreeAddrGPR<InstMIPS32::Mul>; 924 using InstMIPS32Mul = InstMIPS32ThreeAddrGPR<InstMIPS32::Mul>;
913 using InstMIPS32Mul_d = InstMIPS32ThreeAddrFPR<InstMIPS32::Mul_d>; 925 using InstMIPS32Mul_d = InstMIPS32ThreeAddrFPR<InstMIPS32::Mul_d>;
914 using InstMIPS32Mul_s = InstMIPS32ThreeAddrFPR<InstMIPS32::Mul_s>; 926 using InstMIPS32Mul_s = InstMIPS32ThreeAddrFPR<InstMIPS32::Mul_s>;
915 using InstMIPS32Mult = InstMIPS32ThreeAddrGPR<InstMIPS32::Mult>; 927 using InstMIPS32Mult = InstMIPS32ThreeAddrGPR<InstMIPS32::Mult>;
916 using InstMIPS32Multu = InstMIPS32ThreeAddrGPR<InstMIPS32::Multu>; 928 using InstMIPS32Multu = InstMIPS32ThreeAddrGPR<InstMIPS32::Multu>;
917 using InstMIPS32Or = InstMIPS32ThreeAddrGPR<InstMIPS32::Or>; 929 using InstMIPS32Or = InstMIPS32ThreeAddrGPR<InstMIPS32::Or>;
918 using InstMIPS32Ori = InstMIPS32Imm16<InstMIPS32::Ori>; 930 using InstMIPS32Ori = InstMIPS32Imm16<InstMIPS32::Ori>;
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991 template <> void InstMIPS32Mtlo::emit(const Cfg *Func) const; 1003 template <> void InstMIPS32Mtlo::emit(const Cfg *Func) const;
992 template <> void InstMIPS32Mthi::emit(const Cfg *Func) const; 1004 template <> void InstMIPS32Mthi::emit(const Cfg *Func) const;
993 template <> void InstMIPS32Mult::emit(const Cfg *Func) const; 1005 template <> void InstMIPS32Mult::emit(const Cfg *Func) const;
994 template <> void InstMIPS32Multu::emit(const Cfg *Func) const; 1006 template <> void InstMIPS32Multu::emit(const Cfg *Func) const;
995 template <> void InstMIPS32Lui::emit(const Cfg *Func) const; 1007 template <> void InstMIPS32Lui::emit(const Cfg *Func) const;
996 1008
997 } // end of namespace MIPS32 1009 } // end of namespace MIPS32
998 } // end of namespace Ice 1010 } // end of namespace Ice
999 1011
1000 #endif // SUBZERO_SRC_ICEINSTMIPS32_H 1012 #endif // SUBZERO_SRC_ICEINSTMIPS32_H
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