Xfermode: SSE2 implementation of a number of simple transfer modes

Xfermode: SSE2 implementation of a number of simple transfer modes

These modes share some common code and not very complex, so group them
together. This CL yields about 50% performance improvement on desktop
i7-3770. Here are the data:
before:
   Xfermode_Screen   8888:  cmsecs =     30.25   565:  cmsecs =     46.81
 Xfermode_Modulate   8888:  cmsecs =     22.48   565:  cmsecs =     40.06
     Xfermode_Plus   8888:  cmsecs =     21.04   565:  cmsecs =     37.51
      Xfermode_Xor   8888:  cmsecs =     37.18   565:  cmsecs =     52.53
  Xfermode_DstATop   8888:  cmsecs =     28.97   565:  cmsecs =     46.42
  Xfermode_SrcATop   8888:  cmsecs =     29.74   565:  cmsecs =     46.25
   Xfermode_DstOut   8888:  cmsecs =      5.34   565:  cmsecs =     24.53
   Xfermode_SrcOut   8888:  cmsecs =     12.25   565:  cmsecs =     24.39
    Xfermode_DstIn   8888:  cmsecs =      5.30   565:  cmsecs =     24.50
    Xfermode_SrcIn   8888:  cmsecs =     12.05   565:  cmsecs =     25.40
  Xfermode_DstOver   8888:  cmsecs =     12.45   565:  cmsecs =      0.15
  Xfermode_SrcOver   8888:  cmsecs =      2.68   565:  cmsecs =      4.42
after:
   Xfermode_Screen   8888:  cmsecs =     13.68   565:  cmsecs =     21.73
 Xfermode_Modulate   8888:  cmsecs =     13.25   565:  cmsecs =     20.97
     Xfermode_Plus   8888:  cmsecs =      9.77   565:  cmsecs =     16.71
      Xfermode_Xor   8888:  cmsecs =     17.64   565:  cmsecs =     25.62
  Xfermode_DstATop   8888:  cmsecs =     15.99   565:  cmsecs =     23.74
  Xfermode_SrcATop   8888:  cmsecs =     15.69   565:  cmsecs =     23.40
   Xfermode_DstOut   8888:  cmsecs =      4.77   565:  cmsecs =     11.85
   Xfermode_SrcOut   8888:  cmsecs =      4.98   565:  cmsecs =     11.84
    Xfermode_DstIn   8888:  cmsecs =      4.68   565:  cmsecs =     11.72
    Xfermode_SrcIn   8888:  cmsecs =      4.93   565:  cmsecs =     11.79
  Xfermode_DstOver   8888:  cmsecs =      5.04   565:  cmsecs =      0.15
  Xfermode_SrcOver   8888:  cmsecs =      2.69   565:  cmsecs =      4.42

BUG=skia:

Committed: http://code.google.com/p/skia/source/detail?r=14176

[qiankun, 2014-04-10 09:23:57]

PTAL.

[mtklein, 2014-04-11 18:41:53]

lgtm

Some questions, but this LGTM as it stands.

https://codereview.chromium.org/232793002/diff/1/src/opts/SkColor_opts_SSE2.h
File src/opts/SkColor_opts_SSE2.h (right):

https://codereview.chromium.org/232793002/diff/1/src/opts/SkColor_opts_SSE2.h...
src/opts/SkColor_opts_SSE2.h:29: static inline __m128i SkAlphaMulQ_SSE2(const
__m128i& c, const __m128i& scale) {
Is this still the best way to do this with SSE2?   You see we're doing a sort of
4x8-bit SIMD in 32-bit ints, but we have to split them in two because the 8*8
bit multiply results in 16 bits.  Any way to perhaps just do this directly in on
SSE register instead of splitting into rb and ag?  Or I guess that would need a
non-existent _mm_mullo_epi8?

https://codereview.chromium.org/232793002/diff/1/src/opts/SkXfermode_opts_SSE...
File src/opts/SkXfermode_opts_SSE2.cpp (right):

https://codereview.chromium.org/232793002/diff/1/src/opts/SkXfermode_opts_SSE...
src/opts/SkXfermode_opts_SSE2.cpp:151: __m128i b =
saturated_add_SSE2(SkGetPackedB32_SSE2(src),
Any reason to do this one in b-g-r-a order instead of a-r-g-b like the others? 
I'm fine if it's just arbitrary, but if it's important, let's mark it.

[qiankun, 2014-04-14 02:33:00]

Thanks for review, see my reply below. I will check the commit box.

https://codereview.chromium.org/232793002/diff/1/src/opts/SkColor_opts_SSE2.h
File src/opts/SkColor_opts_SSE2.h (right):

https://codereview.chromium.org/232793002/diff/1/src/opts/SkColor_opts_SSE2.h...
src/opts/SkColor_opts_SSE2.h:29: static inline __m128i SkAlphaMulQ_SSE2(const
__m128i& c, const __m128i& scale) {
On 2014/04/11 18:41:54, mtklein wrote:
> Is this still the best way to do this with SSE2?   You see we're doing a sort
of
> 4x8-bit SIMD in 32-bit ints, but we have to split them in two because the 8*8
> bit multiply results in 16 bits.  Any way to perhaps just do this directly in
on
> SSE register instead of splitting into rb and ag?  Or I guess that would need
a
> non-existent _mm_mullo_epi8?

Unfortunately, there is no 8-bits multiply funciton in SSE2 intrinsics. So keep
the current SSE2 implementation now.

https://codereview.chromium.org/232793002/diff/1/src/opts/SkXfermode_opts_SSE...
File src/opts/SkXfermode_opts_SSE2.cpp (right):

https://codereview.chromium.org/232793002/diff/1/src/opts/SkXfermode_opts_SSE...
src/opts/SkXfermode_opts_SSE2.cpp:151: __m128i b =
saturated_add_SSE2(SkGetPackedB32_SSE2(src),
On 2014/04/11 18:41:54, mtklein wrote:
> Any reason to do this one in b-g-r-a order instead of a-r-g-b like the others?

> I'm fine if it's just arbitrary, but if it's important, let's mark it.

No special reason for the b-g-r-a order, I just followed this order in the
portable version plus_modeproc() in SkXfermode.cpp.

[qiankun, 2014-04-14 02:33:32]

The CQ bit was checked by qiankun.miao@intel.com

[commit-bot: I haz the power, 2014-04-14 02:33:39]

CQ is trying da patch. Follow status at
https://skia-tree-status.appspot.com/cq/qiankun.miao@intel.com/232793002/1

[commit-bot: I haz the power, 2014-04-14 14:54:24]

Change committed as 14176