Chromium Code Reviews Chromium Code Reviews
Issue 2324903002:
Subzero, MIPS32: Handling fptrunc and fpext casting (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master| OLD | NEW |
|---|---|
| 1 ; This tries to be a comprehensive test of f32 and f64 convert operations. | 1 ; This tries to be a comprehensive test of f32 and f64 convert operations. |
| 2 ; The CHECK lines are only checking for basic instruction patterns | 2 ; The CHECK lines are only checking for basic instruction patterns |
| 3 ; that should be present regardless of the optimization level, so | 3 ; that should be present regardless of the optimization level, so |
| 4 ; there are no special OPTM1 match lines. | 4 ; there are no special OPTM1 match lines. |
| 5 | 5 |
| 6 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s | 6 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s |
| 7 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s | 7 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s |
| 8 | 8 |
| 9 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ | 9 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ |
| 10 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ | 10 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ |
| 11 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ | 11 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ |
| 12 ; RUN: --check-prefix=ARM32 | 12 ; RUN: --check-prefix=ARM32 |
| 13 | 13 |
| 14 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ | 14 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ |
| 15 ; RUN: --target arm32 -i %s --args -Om1 --skip-unimplemented \ | 15 ; RUN: --target arm32 -i %s --args -Om1 --skip-unimplemented \ |
| 16 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ | 16 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ |
| 17 ; RUN: --check-prefix=ARM32 | 17 ; RUN: --check-prefix=ARM32 |
| 18 | 18 |
| 19 ; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i --filetype=asm \ | |
|
Jim Stichnoth
2016/09/11 14:08:19
80-col
(I went ahead and fixed this myself)
| |
| 20 ; RUN: --target mips32 -i %s --args -Om1 --skip-unimplemented \ | |
| 21 ; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \ | |
| 22 ; RUN: --check-prefix=MIPS32 | |
| 23 | |
| 19 define internal float @fptrunc(double %a) { | 24 define internal float @fptrunc(double %a) { |
| 20 entry: | 25 entry: |
| 21 %conv = fptrunc double %a to float | 26 %conv = fptrunc double %a to float |
| 22 ret float %conv | 27 ret float %conv |
| 23 } | 28 } |
| 24 ; CHECK-LABEL: fptrunc | 29 ; CHECK-LABEL: fptrunc |
| 25 ; CHECK: cvtsd2ss | 30 ; CHECK: cvtsd2ss |
| 26 ; CHECK: fld | 31 ; CHECK: fld |
| 27 ; ARM32-LABEL: fptrunc | 32 ; ARM32-LABEL: fptrunc |
| 28 ; ARM32: vcvt.f32.f64 {{s[0-9]+}}, {{d[0-9]+}} | 33 ; ARM32: vcvt.f32.f64 {{s[0-9]+}}, {{d[0-9]+}} |
| 34 ; MIPS32-LABEL: fptrunc | |
| 35 ; MIPS32: cvt.s.d | |
| 29 | 36 |
| 30 define internal double @fpext(float %a) { | 37 define internal double @fpext(float %a) { |
| 31 entry: | 38 entry: |
| 32 %conv = fpext float %a to double | 39 %conv = fpext float %a to double |
| 33 ret double %conv | 40 ret double %conv |
| 34 } | 41 } |
| 35 ; CHECK-LABEL: fpext | 42 ; CHECK-LABEL: fpext |
| 36 ; CHECK: cvtss2sd | 43 ; CHECK: cvtss2sd |
| 37 ; CHECK: fld | 44 ; CHECK: fld |
| 38 ; ARM32-LABEL: fpext | 45 ; ARM32-LABEL: fpext |
| 39 ; ARM32: vcvt.f64.f32 {{d[0-9]+}}, {{s[0-9]+}} | 46 ; ARM32: vcvt.f64.f32 {{d[0-9]+}}, {{s[0-9]+}} |
| 47 ; MIPS32-LABEL: fpext | |
| 48 ; MIPS32: cvt.d.s | |
| 40 | 49 |
| 41 define internal i64 @doubleToSigned64(double %a) { | 50 define internal i64 @doubleToSigned64(double %a) { |
| 42 entry: | 51 entry: |
| 43 %conv = fptosi double %a to i64 | 52 %conv = fptosi double %a to i64 |
| 44 ret i64 %conv | 53 ret i64 %conv |
| 45 } | 54 } |
| 46 ; CHECK-LABEL: doubleToSigned64 | 55 ; CHECK-LABEL: doubleToSigned64 |
| 47 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f64_i64 | 56 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f64_i64 |
| 48 ; ARM32-LABEL: doubleToSigned64 | 57 ; ARM32-LABEL: doubleToSigned64 |
| 49 ; TODO(jpp): implement this test. | 58 ; TODO(jpp): implement this test. |
| (...skipping 538 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 588 %conv = bitcast i64 9035768 to double | 597 %conv = bitcast i64 9035768 to double |
| 589 ret double %conv | 598 ret double %conv |
| 590 } | 599 } |
| 591 ; CHECK-LABEL: int64BitcastToDoubleConst | 600 ; CHECK-LABEL: int64BitcastToDoubleConst |
| 592 ; CHECK: mov | 601 ; CHECK: mov |
| 593 ; ARM32-LABEL: int64BitcastToDoubleConst | 602 ; ARM32-LABEL: int64BitcastToDoubleConst |
| 594 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336 | 603 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336 |
| 595 ; ARM32-DAG: movt [[REG0]], #137 | 604 ; ARM32-DAG: movt [[REG0]], #137 |
| 596 ; ARM32-DAG: mov [[REG1:r[0-9]+]], #0 | 605 ; ARM32-DAG: mov [[REG1:r[0-9]+]], #0 |
| 597 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]] | 606 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]] |
| OLD | NEW |
