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Side by Side Diff: src/IceTargetLoweringMIPS32.cpp

Issue 2324903002: Subzero, MIPS32: Handling fptrunc and fpext casting (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 3 months ago
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1 // 1 //
2 // The Subzero Code Generator 2 // The Subzero Code Generator
3 // 3 //
4 // This file is distributed under the University of Illinois Open Source 4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details. 5 // License. See LICENSE.TXT for details.
6 // 6 //
7 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
8 /// 8 ///
9 /// \file 9 /// \file
10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
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2011 } 2011 }
2012 case InstCast::Trunc: { 2012 case InstCast::Trunc: {
2013 if (Src0Ty == IceType_i64) 2013 if (Src0Ty == IceType_i64)
2014 Src0 = loOperand(Src0); 2014 Src0 = loOperand(Src0);
2015 Variable *Src0R = legalizeToReg(Src0); 2015 Variable *Src0R = legalizeToReg(Src0);
2016 Variable *T = makeReg(DestTy); 2016 Variable *T = makeReg(DestTy);
2017 _mov(T, Src0R); 2017 _mov(T, Src0R);
2018 _mov(Dest, T); 2018 _mov(Dest, T);
2019 break; 2019 break;
2020 } 2020 }
2021 case InstCast::Fptrunc: 2021 case InstCast::Fptrunc: {
2022 // Use _cvt_d_s 2022 assert(Dest->getType() == IceType_f32);
2023 UnimplementedLoweringError(this, Instr); 2023 assert(Src0->getType() == IceType_f64);
2024 break; 2024 auto *DestR = legalizeToReg(Dest);
2025 case InstCast::Fpext: { 2025 auto *Src0R = legalizeToReg(Src0);
2026 // Use _cvt_s_d 2026 _cvt_s_d(DestR, Src0R);
2027 UnimplementedLoweringError(this, Instr); 2027 _mov(Dest, DestR);
2028 break; 2028 break;
2029 } 2029 }
2030 case InstCast::Fptosi: 2030 case InstCast::Fpext: {
2031 assert(Dest->getType() == IceType_f64);
2032 assert(Src0->getType() == IceType_f32);
2033 auto *DestR = legalizeToReg(Dest);
2034 auto *Src0R = legalizeToReg(Src0);
2035 _cvt_d_s(DestR, Src0R);
2036 _mov(Dest, DestR);
2037 break;
2038 }
2039 case InstCast::Fptosi: //
2031 UnimplementedLoweringError(this, Instr); 2040 UnimplementedLoweringError(this, Instr);
2032 break; 2041 break;
2033 case InstCast::Fptoui: 2042 case InstCast::Fptoui:
2034 UnimplementedLoweringError(this, Instr); 2043 UnimplementedLoweringError(this, Instr);
2035 break; 2044 break;
2036 case InstCast::Sitofp: 2045 case InstCast::Sitofp: //
2037 UnimplementedLoweringError(this, Instr); 2046 UnimplementedLoweringError(this, Instr);
2038 break; 2047 break;
2039 case InstCast::Uitofp: { 2048 case InstCast::Uitofp: {
2040 UnimplementedLoweringError(this, Instr); 2049 UnimplementedLoweringError(this, Instr);
2041 break; 2050 break;
2042 } 2051 }
2043 case InstCast::Bitcast: { 2052 case InstCast::Bitcast: {
2044 UnimplementedLoweringError(this, Instr); 2053 UnimplementedLoweringError(this, Instr);
2045 break; 2054 break;
2046 } 2055 }
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2729 Str << "\t.set\t" 2738 Str << "\t.set\t"
2730 << "nomips16\n"; 2739 << "nomips16\n";
2731 } 2740 }
2732 2741
2733 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; 2742 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
2734 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; 2743 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
2735 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; 2744 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
2736 2745
2737 } // end of namespace MIPS32 2746 } // end of namespace MIPS32
2738 } // end of namespace Ice 2747 } // end of namespace Ice
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