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1 #!/usr/bin/env perl | 1 #!/usr/bin/env perl |
2 ## | 2 ## |
3 ## Copyright (c) 2013 The WebM project authors. All Rights Reserved. | 3 ## Copyright (c) 2013 The WebM project authors. All Rights Reserved. |
4 ## | 4 ## |
5 ## Use of this source code is governed by a BSD-style license | 5 ## Use of this source code is governed by a BSD-style license |
6 ## that can be found in the LICENSE file in the root of the source | 6 ## that can be found in the LICENSE file in the root of the source |
7 ## tree. An additional intellectual property rights grant can be found | 7 ## tree. An additional intellectual property rights grant can be found |
8 ## in the file PATENTS. All contributing project authors may | 8 ## in the file PATENTS. All contributing project authors may |
9 ## be found in the AUTHORS file in the root of the source tree. | 9 ## be found in the AUTHORS file in the root of the source tree. |
10 ## | 10 ## |
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
44 # This converts "ldrne r4, [src, -pstep, lsl #1]" into | 44 # This converts "ldrne r4, [src, -pstep, lsl #1]" into |
45 # "subne src, src, pstep, lsl #1", "ldrne r4, [src]", | 45 # "subne src, src, pstep, lsl #1", "ldrne r4, [src]", |
46 # "addne src, src, pstep, lsl #1". In a couple of cases where | 46 # "addne src, src, pstep, lsl #1". In a couple of cases where |
47 # this is used, it's used for two subsequent load instructions, | 47 # this is used, it's used for two subsequent load instructions, |
48 # where a hand-written version of it could merge two subsequent | 48 # where a hand-written version of it could merge two subsequent |
49 # add and sub instructions. | 49 # add and sub instructions. |
50 s/^(\s*)((ldr|str|pld)(ne)?)(\s+)(r\d+,\s*)?\[(\w+), -([^\]]+)\]/$1sub$4$5$7
, $7, $8\n$1$2$5$6\[$7\]\n$1add$4$5$7, $7, $8/g; | 50 s/^(\s*)((ldr|str|pld)(ne)?)(\s+)(r\d+,\s*)?\[(\w+), -([^\]]+)\]/$1sub$4$5$7
, $7, $8\n$1$2$5$6\[$7\]\n$1add$4$5$7, $7, $8/g; |
51 | 51 |
52 # Convert register post indexing to a separate add instruction. | 52 # Convert register post indexing to a separate add instruction. |
53 # This converts "ldrneb r9, [r0], r2" into "ldrneb r9, [r0]", | 53 # This converts "ldrneb r9, [r0], r2" into "ldrneb r9, [r0]", |
54 # "add r0, r2". | 54 # "addne r0, r0, r2". |
55 s/^(\s*)((ldr|str)(ne)?[bhd]?)(\s+)(\w+),(\s*\w+,)?\s*\[(\w+)\],\s*(\w+)/$1$
2$5$6,$7 [$8]\n$1add$4$5$8, $8, $9/g; | 55 s/^(\s*)((ldr|str)(ne)?[bhd]?)(\s+)(\w+),(\s*\w+,)?\s*\[(\w+)\],\s*(\w+)/$1$
2$5$6,$7 [$8]\n$1add$4$5$8, $8, $9/g; |
56 | 56 |
57 # Convert a conditional addition to the pc register into a series of | 57 # Convert a conditional addition to the pc register into a series of |
58 # instructions. This converts "addlt pc, pc, r3, lsl #2" into | 58 # instructions. This converts "addlt pc, pc, r3, lsl #2" into |
59 # "itttt lt", "movlt.n r12, pc", "addlt.w r12, #12", | 59 # "itttt lt", "movlt.n r12, pc", "addlt.w r12, #12", |
60 # "addlt.w r12, r12, r3, lsl #2", "movlt.n pc, r12". | 60 # "addlt.w r12, r12, r3, lsl #2", "movlt.n pc, r12". |
61 # This assumes that r12 is free at this point. | 61 # This assumes that r12 is free at this point. |
62 s/^(\s*)addlt(\s+)pc,\s*pc,\s*(\w+),\s*lsl\s*#(\d+)/$1itttt$2lt\n$1movlt.n$2
r12, pc\n$1addlt.w$2r12, #12\n$1addlt.w$2r12, r12, $3, lsl #($4-$branch_shift_of
fset)\n$1movlt.n$2pc, r12/g; | 62 s/^(\s*)addlt(\s+)pc,\s*pc,\s*(\w+),\s*lsl\s*#(\d+)/$1itttt$2lt\n$1movlt.n$2
r12, pc\n$1addlt.w$2r12, #12\n$1addlt.w$2r12, r12, $3, lsl #($4-$branch_shift_of
fset)\n$1movlt.n$2pc, r12/g; |
63 | 63 |
64 # Convert "mov pc, lr" into "bx lr", since the former only works | 64 # Convert "mov pc, lr" into "bx lr", since the former only works |
65 # for switching from arm to thumb (and only in armv7), but not | 65 # for switching from arm to thumb (and only in armv7), but not |
66 # from thumb to arm. | 66 # from thumb to arm. |
67 s/mov(\s*)pc\s*,\s*lr/bx$1lr/g; | 67 s/mov(\s*)pc\s*,\s*lr/bx$1lr/g; |
68 } | 68 } |
69 | 69 |
70 1; | 70 1; |
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