Subzero, MIPS32: Introduction of genTargetHelperCallFor

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 390 matching lines @@
 ; CHECK: call {{.*}} R_{{.*}}    __divdi3
 
 ; OPTM1-LABEL: div64BitSigned
 ; OPTM1: call {{.*}} R_{{.*}}    __divdi3
 ;
 ; ARM32-LABEL: div64BitSigned
 ; ARM32: orrs {{r.*}}, {{r.*}}
 ; ARM32: bne
 ; ARM32: bl {{.*}} __divdi3
 
+; MIPS32-LABEL: div64BitSigned
+; MIPS32: jal {{.*}} __divdi3
+
 define internal i64 @div64BitSignedConst(i64 %a) {
 entry:
   %div = sdiv i64 %a, 12345678901234
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitSignedConst
 ; CHECK: mov     DWORD PTR [esp+0xc],0xb3a
 ; CHECK: mov     DWORD PTR [esp+0x8],0x73ce2ff2
 ; CHECK: call {{.*}} R_{{.*}}    __divdi3
 ;
 ; OPTM1-LABEL: div64BitSignedConst
 ; OPTM1: mov     DWORD PTR [esp+0xc],0xb3a
 ; OPTM1: mov     DWORD PTR [esp+0x8],0x73ce2ff2
 ; OPTM1: call {{.*}} R_{{.*}}    __divdi3
 ;
 ; ARM32-LABEL: div64BitSignedConst
 ; For a constant, we should be able to optimize-out the divide by zero check.
 ; ARM32-NOT: orrs
 ; ARM32: movw {{.*}} ; 0x2ff2
 ; ARM32: movt {{.*}} ; 0x73ce
 ; ARM32: movw {{.*}} ; 0xb3a
 ; ARM32: bl {{.*}} __divdi3
 
+; MIPS32-LABEL: div64BitSignedConst
+; MIPS32: jal {{.*}} __divdi3
+
 define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %div = udiv i64 %a, %b
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitUnsigned
 ; CHECK: call {{.*}} R_{{.*}}    __udivdi3
 ;
 ; OPTM1-LABEL: div64BitUnsigned
 ; OPTM1: call {{.*}} R_{{.*}}    __udivdi3
 ;
 ; ARM32-LABEL: div64BitUnsigned
 ; ARM32: orrs {{r.*}}, {{r.*}}
 ; ARM32: bne
 ; ARM32: bl {{.*}} __udivdi3
 
+; MIPS32-LABEL: div64BitUnsigned
+; MIPS32: jal {{.*}} __udivdi3
+
 define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
 entry:
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
 ; CHECK-LABEL: rem64BitSigned
 ; CHECK: call {{.*}} R_{{.*}}    __moddi3
 ;
 ; OPTM1-LABEL: rem64BitSigned
 ; OPTM1: call {{.*}} R_{{.*}}    __moddi3
 ;
 ; ARM32-LABEL: rem64BitSigned
 ; ARM32: orrs {{r.*}}, {{r.*}}
 ; ARM32: bne
 ; ARM32: bl {{.*}} __moddi3
 
+; MIPS32-LABEL: rem64BitSigned
+; MIPS32: jal {{.*}} __moddi3
+
 define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
 ; CHECK-LABEL: rem64BitUnsigned
 ; CHECK: call {{.*}} R_{{.*}}    __umoddi3
 ;
 ; OPTM1-LABEL: rem64BitUnsigned
 ; OPTM1: call {{.*}} R_{{.*}}    __umoddi3
 ;
 ; ARM32-LABEL: rem64BitUnsigned
 ; ARM32: orrs {{r.*}}, {{r.*}}
 ; ARM32: bne
 ; ARM32: bl {{.*}} __umoddi3
 
+; MIPS32-LABEL: rem64BitUnsigned
+; MIPS32: jal {{.*}} __umoddi3
+
 define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   ret i64 %shl
 }
 ; CHECK-LABEL: shl64BitSigned
 ; CHECK: shld
 ; CHECK: shl e
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
@@ skipping 1567 matching lines @@
   %s = lshr i64 %a, 40
   %t = trunc i64 %s to i32
   %r = sub i32 %t, 1
   ret i32 %r
 ; ARM32-LABEL: subOneToUpperAfterShift
 ; ARM32: subs
 ; ARM32: sbc
 ; ARM32: lsr
 ; ARM32: sub
 }