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1 ; This tries to be a comprehensive test of f32 and f64 convert operations. | 1 ; This tries to be a comprehensive test of f32 and f64 convert operations. |
2 ; The CHECK lines are only checking for basic instruction patterns | 2 ; The CHECK lines are only checking for basic instruction patterns |
3 ; that should be present regardless of the optimization level, so | 3 ; that should be present regardless of the optimization level, so |
4 ; there are no special OPTM1 match lines. | 4 ; there are no special OPTM1 match lines. |
5 | 5 |
6 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s | 6 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s |
7 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s | 7 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s |
8 | 8 |
9 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ | 9 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ |
10 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ | 10 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ |
11 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ | 11 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ |
12 ; RUN: --check-prefix=ARM32 | 12 ; RUN: --check-prefix=ARM32 |
13 | 13 |
14 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ | 14 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ |
15 ; RUN: --target arm32 -i %s --args -Om1 --skip-unimplemented \ | 15 ; RUN: --target arm32 -i %s --args -Om1 --skip-unimplemented \ |
16 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ | 16 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ |
17 ; RUN: --check-prefix=ARM32 | 17 ; RUN: --check-prefix=ARM32 |
18 | 18 |
19 ; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \ | 19 ; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \ |
20 ; RUN: --filetype=asm --target mips32 -i %s --args -Om1 --skip-unimplemented \ | 20 ; RUN: --filetype=asm --target mips32 -i %s --args -Om1 --skip-unimplemented \ |
21 ; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \ | 21 ; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \ |
22 ; RUN: --check-prefix=MIPS32 | 22 ; RUN: --check-prefix=MIPS32 |
23 | 23 |
| 24 ; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \ |
| 25 ; RUN: --filetype=asm --target mips32 -i %s --args -O2 --skip-unimplemented \ |
| 26 ; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \ |
| 27 ; RUN: --check-prefix=MIPS32O2 |
| 28 |
24 define internal float @fptrunc(double %a) { | 29 define internal float @fptrunc(double %a) { |
25 entry: | 30 entry: |
26 %conv = fptrunc double %a to float | 31 %conv = fptrunc double %a to float |
27 ret float %conv | 32 ret float %conv |
28 } | 33 } |
29 ; CHECK-LABEL: fptrunc | 34 ; CHECK-LABEL: fptrunc |
30 ; CHECK: cvtsd2ss | 35 ; CHECK: cvtsd2ss |
31 ; CHECK: fld | 36 ; CHECK: fld |
32 ; ARM32-LABEL: fptrunc | 37 ; ARM32-LABEL: fptrunc |
33 ; ARM32: vcvt.f32.f64 {{s[0-9]+}}, {{d[0-9]+}} | 38 ; ARM32: vcvt.f32.f64 {{s[0-9]+}}, {{d[0-9]+}} |
34 ; MIPS32-LABEL: fptrunc | 39 ; MIPS32-LABEL: fptrunc |
35 ; MIPS32: cvt.s.d | 40 ; MIPS32: cvt.s.d |
| 41 ; MIPS32O2-LABEL: fptrunc |
| 42 ; MIPS32O2: cvt.s.d |
36 | 43 |
37 define internal double @fpext(float %a) { | 44 define internal double @fpext(float %a) { |
38 entry: | 45 entry: |
39 %conv = fpext float %a to double | 46 %conv = fpext float %a to double |
40 ret double %conv | 47 ret double %conv |
41 } | 48 } |
42 ; CHECK-LABEL: fpext | 49 ; CHECK-LABEL: fpext |
43 ; CHECK: cvtss2sd | 50 ; CHECK: cvtss2sd |
44 ; CHECK: fld | 51 ; CHECK: fld |
45 ; ARM32-LABEL: fpext | 52 ; ARM32-LABEL: fpext |
46 ; ARM32: vcvt.f64.f32 {{d[0-9]+}}, {{s[0-9]+}} | 53 ; ARM32: vcvt.f64.f32 {{d[0-9]+}}, {{s[0-9]+}} |
47 ; MIPS32-LABEL: fpext | 54 ; MIPS32-LABEL: fpext |
48 ; MIPS32: cvt.d.s | 55 ; MIPS32: cvt.d.s |
| 56 ; MIPS32O2-LABEL: fpext |
| 57 ; MIPS32O2: cvt.d.s |
49 | 58 |
50 define internal i64 @doubleToSigned64(double %a) { | 59 define internal i64 @doubleToSigned64(double %a) { |
51 entry: | 60 entry: |
52 %conv = fptosi double %a to i64 | 61 %conv = fptosi double %a to i64 |
53 ret i64 %conv | 62 ret i64 %conv |
54 } | 63 } |
55 ; CHECK-LABEL: doubleToSigned64 | 64 ; CHECK-LABEL: doubleToSigned64 |
56 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f64_i64 | 65 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f64_i64 |
57 ; ARM32-LABEL: doubleToSigned64 | 66 ; ARM32-LABEL: doubleToSigned64 |
58 ; TODO(jpp): implement this test. | 67 ; TODO(jpp): implement this test. |
| 68 ; MIPS32-LABEL: doubleToSigned64 |
| 69 ; MIPS32: jal __Sz_fptosi_f64_i64 |
| 70 ; MIPS32O2-LABEL: doubleToSigned64 |
| 71 ; MIPS32O2: jal __Sz_fptosi_f64_i64 |
59 | 72 |
60 define internal i64 @floatToSigned64(float %a) { | 73 define internal i64 @floatToSigned64(float %a) { |
61 entry: | 74 entry: |
62 %conv = fptosi float %a to i64 | 75 %conv = fptosi float %a to i64 |
63 ret i64 %conv | 76 ret i64 %conv |
64 } | 77 } |
65 ; CHECK-LABEL: floatToSigned64 | 78 ; CHECK-LABEL: floatToSigned64 |
66 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f32_i64 | 79 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f32_i64 |
67 ; ARM32-LABEL: floatToSigned64 | 80 ; ARM32-LABEL: floatToSigned64 |
68 ; TODO(jpp): implement this test. | 81 ; TODO(jpp): implement this test. |
| 82 ; MIPS32-LABEL: floatToSigned64 |
| 83 ; MIPS32: jal __Sz_fptosi_f32_i64 |
| 84 ; MIPS32O2-LABEL: floatToSigned64 |
| 85 ; MIPS32O2: jal __Sz_fptosi_f32_i64 |
69 | 86 |
70 define internal i64 @doubleToUnsigned64(double %a) { | 87 define internal i64 @doubleToUnsigned64(double %a) { |
71 entry: | 88 entry: |
72 %conv = fptoui double %a to i64 | 89 %conv = fptoui double %a to i64 |
73 ret i64 %conv | 90 ret i64 %conv |
74 } | 91 } |
75 ; CHECK-LABEL: doubleToUnsigned64 | 92 ; CHECK-LABEL: doubleToUnsigned64 |
76 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f64_i64 | 93 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f64_i64 |
77 ; ARM32-LABEL: doubleToUnsigned64 | 94 ; ARM32-LABEL: doubleToUnsigned64 |
78 ; TODO(jpp): implement this test. | 95 ; TODO(jpp): implement this test. |
| 96 ; MIPS32-LABEL: doubleToUnsigned64 |
| 97 ; MIPS32: jal __Sz_fptoui_f64_i64 |
| 98 ; MIPS32O2-LABEL: doubleToUnsigned64 |
| 99 ; MIPS32O2: jal __Sz_fptoui_f64_i64 |
79 | 100 |
80 define internal i64 @floatToUnsigned64(float %a) { | 101 define internal i64 @floatToUnsigned64(float %a) { |
81 entry: | 102 entry: |
82 %conv = fptoui float %a to i64 | 103 %conv = fptoui float %a to i64 |
83 ret i64 %conv | 104 ret i64 %conv |
84 } | 105 } |
85 ; CHECK-LABEL: floatToUnsigned64 | 106 ; CHECK-LABEL: floatToUnsigned64 |
86 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f32_i64 | 107 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f32_i64 |
87 ; ARM32-LABEL: floatToUnsigned64 | 108 ; ARM32-LABEL: floatToUnsigned64 |
88 ; TODO(jpp): implement this test. | 109 ; TODO(jpp): implement this test. |
| 110 ; MIPS32-LABEL: floatToUnsigned64 |
| 111 ; MIPS32: jal __Sz_fptoui_f32_i64 |
| 112 ; MIPS32O2-LABEL: floatToUnsigned64 |
| 113 ; MIPS32O2: jal __Sz_fptoui_f32_i64 |
89 | 114 |
90 define internal i32 @doubleToSigned32(double %a) { | 115 define internal i32 @doubleToSigned32(double %a) { |
91 entry: | 116 entry: |
92 %conv = fptosi double %a to i32 | 117 %conv = fptosi double %a to i32 |
93 ret i32 %conv | 118 ret i32 %conv |
94 } | 119 } |
95 ; CHECK-LABEL: doubleToSigned32 | 120 ; CHECK-LABEL: doubleToSigned32 |
96 ; CHECK: cvttsd2si | 121 ; CHECK: cvttsd2si |
97 ; ARM32-LABEL: doubleToSigned32 | 122 ; ARM32-LABEL: doubleToSigned32 |
98 ; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} | 123 ; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} |
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115 define internal i32 @floatToSigned32(float %a) { | 140 define internal i32 @floatToSigned32(float %a) { |
116 entry: | 141 entry: |
117 %conv = fptosi float %a to i32 | 142 %conv = fptosi float %a to i32 |
118 ret i32 %conv | 143 ret i32 %conv |
119 } | 144 } |
120 ; CHECK-LABEL: floatToSigned32 | 145 ; CHECK-LABEL: floatToSigned32 |
121 ; CHECK: cvttss2si | 146 ; CHECK: cvttss2si |
122 ; ARM32-LABEL: floatToSigned32 | 147 ; ARM32-LABEL: floatToSigned32 |
123 ; ARM32-DAG: vcvt.s32.f32 [[REG:s[0-9]+]], {{s[0-9]+}} | 148 ; ARM32-DAG: vcvt.s32.f32 [[REG:s[0-9]+]], {{s[0-9]+}} |
124 ; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] | 149 ; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] |
| 150 ; MIPS32-LABEL: floatToSigned32 |
| 151 ; MIPS32: trunc.w.s $f{{.*}}, $f{{.*}} |
| 152 ; MIPS32O2-LABEL: floatToSigned32 |
| 153 ; MIPS32O2: trunc.w.s $[[REG:f[0-9]+]], $f{{.*}} |
| 154 ; MIPS32O2: mfc1 $v0, $[[REG]] |
125 | 155 |
126 define internal i32 @doubleToUnsigned32(double %a) { | 156 define internal i32 @doubleToUnsigned32(double %a) { |
127 entry: | 157 entry: |
128 %conv = fptoui double %a to i32 | 158 %conv = fptoui double %a to i32 |
129 ret i32 %conv | 159 ret i32 %conv |
130 } | 160 } |
131 ; CHECK-LABEL: doubleToUnsigned32 | 161 ; CHECK-LABEL: doubleToUnsigned32 |
132 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f64_i32 | 162 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f64_i32 |
133 ; ARM32-LABEL: doubleToUnsigned32 | 163 ; ARM32-LABEL: doubleToUnsigned32 |
134 ; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]+]], {{d[0-9]+}} | 164 ; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]+]], {{d[0-9]+}} |
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375 entry: | 405 entry: |
376 %conv = sitofp i32 %a to float | 406 %conv = sitofp i32 %a to float |
377 ret float %conv | 407 ret float %conv |
378 } | 408 } |
379 ; CHECK-LABEL: signed32ToFloat | 409 ; CHECK-LABEL: signed32ToFloat |
380 ; CHECK: cvtsi2ss | 410 ; CHECK: cvtsi2ss |
381 ; CHECK: fld | 411 ; CHECK: fld |
382 ; ARM32-LABEL: signed32ToFloat | 412 ; ARM32-LABEL: signed32ToFloat |
383 ; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}} | 413 ; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}} |
384 ; ARM32-DAG: vcvt.f32.s32 {{s[0-9]+}}, [[SRC]] | 414 ; ARM32-DAG: vcvt.f32.s32 {{s[0-9]+}}, [[SRC]] |
| 415 ; MIPS32-LABEL: signed32ToFloat |
| 416 ; MIPS32: cvt.s.w $f{{.*}}, $f{{.*}} |
| 417 ; MIPS32O2-LABEL: signed32ToFloat |
| 418 ; MIPS32O2: mtc1 $a0, $[[REG:f[0-9]+]] |
| 419 ; MIPS32O2: cvt.s.w $f{{.*}}, $[[REG]] |
385 | 420 |
386 define internal double @unsigned32ToDouble(i32 %a) { | 421 define internal double @unsigned32ToDouble(i32 %a) { |
387 entry: | 422 entry: |
388 %conv = uitofp i32 %a to double | 423 %conv = uitofp i32 %a to double |
389 ret double %conv | 424 ret double %conv |
390 } | 425 } |
391 ; CHECK-LABEL: unsigned32ToDouble | 426 ; CHECK-LABEL: unsigned32ToDouble |
392 ; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i32_f64 | 427 ; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i32_f64 |
393 ; CHECK: fstp QWORD | 428 ; CHECK: fstp QWORD |
394 ; ARM32-LABEL: unsigned32ToDouble | 429 ; ARM32-LABEL: unsigned32ToDouble |
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597 %conv = bitcast i64 9035768 to double | 632 %conv = bitcast i64 9035768 to double |
598 ret double %conv | 633 ret double %conv |
599 } | 634 } |
600 ; CHECK-LABEL: int64BitcastToDoubleConst | 635 ; CHECK-LABEL: int64BitcastToDoubleConst |
601 ; CHECK: mov | 636 ; CHECK: mov |
602 ; ARM32-LABEL: int64BitcastToDoubleConst | 637 ; ARM32-LABEL: int64BitcastToDoubleConst |
603 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336 | 638 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336 |
604 ; ARM32-DAG: movt [[REG0]], #137 | 639 ; ARM32-DAG: movt [[REG0]], #137 |
605 ; ARM32-DAG: mov [[REG1:r[0-9]+]], #0 | 640 ; ARM32-DAG: mov [[REG1:r[0-9]+]], #0 |
606 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]] | 641 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]] |
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