[SubZero] Implement GP to/from FP moves for MIPS

tests_lit/llvm2ice_tests/fp.convert.ll

 ; This tries to be a comprehensive test of f32 and f64 convert operations.
 ; The CHECK lines are only checking for basic instruction patterns
 ; that should be present regardless of the optimization level, so
 ; there are no special OPTM1 match lines.
 
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
 
 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
 ; RUN:   --target arm32 -i %s --args -O2 --skip-unimplemented \
 ; RUN:   | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
 ; RUN:   --check-prefix=ARM32
 
 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
 ; RUN:   --target arm32 -i %s --args -Om1 --skip-unimplemented \
 ; RUN:   | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
 ; RUN:   --check-prefix=ARM32
 
+; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
+; RUN:   --filetype=asm --target mips32 -i %s --args -O2 --skip-unimplemented \
+; RUN:   | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
+; RUN:   --check-prefix=MIPS32
+
 define internal float @fptrunc(double %a) {
 entry:
   %conv = fptrunc double %a to float
   ret float %conv
 }
 ; CHECK-LABEL: fptrunc
 ; CHECK: cvtsd2ss
 ; CHECK: fld
 ; ARM32-LABEL: fptrunc
 ; ARM32: vcvt.f32.f64 {{s[0-9]+}}, {{d[0-9]+}}
@@ skipping 77 matching lines @@
 define internal i32 @floatToSigned32(float %a) {
 entry:
   %conv = fptosi float %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: floatToSigned32
 ; CHECK: cvttss2si
 ; ARM32-LABEL: floatToSigned32
 ; ARM32-DAG: vcvt.s32.f32 [[REG:s[0-9]+]], {{s[0-9]+}}
 ; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
+; MIPS32-LABEL: floatToSigned32
+; MIPS32: trunc.w.s $f12, $f12
+; MIPS32: mfc1 $v0, $f12
 
 define internal i32 @doubleToUnsigned32(double %a) {
 entry:
   %conv = fptoui double %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: doubleToUnsigned32
 ; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f64_i32
 ; ARM32-LABEL: doubleToUnsigned32
 ; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]+]], {{d[0-9]+}}
@@ skipping 240 matching lines @@
 entry:
   %conv = sitofp i32 %a to float
   ret float %conv
 }
 ; CHECK-LABEL: signed32ToFloat
 ; CHECK: cvtsi2ss
 ; CHECK: fld
 ; ARM32-LABEL: signed32ToFloat
 ; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}}
 ; ARM32-DAG: vcvt.f32.s32 {{s[0-9]+}}, [[SRC]]
+; MIPS32-LABEL: signed32ToFloat
+; MIPS32: mtc1 $a0, $f0
+; MIPS32: cvt.s.w $f0, $f0
 
 define internal double @unsigned32ToDouble(i32 %a) {
 entry:
   %conv = uitofp i32 %a to double
   ret double %conv
 }
 ; CHECK-LABEL: unsigned32ToDouble
 ; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i32_f64
 ; CHECK: fstp QWORD
 ; ARM32-LABEL: unsigned32ToDouble
@@ skipping 202 matching lines @@
   %conv = bitcast i64 9035768 to double
   ret double %conv
 }
 ; CHECK-LABEL: int64BitcastToDoubleConst
 ; CHECK: mov
 ; ARM32-LABEL: int64BitcastToDoubleConst
 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336
 ; ARM32-DAG: movt [[REG0]], #137
 ; ARM32-DAG: mov [[REG1:r[0-9]+]], #0
 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]