[SubZero] Implement GP to/from FP moves for MIPS

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 1059 matching lines @@
 
   Operand *Src = MovInstr->getSrc(0);
   const Type SrcTy = Src->getType();
   (void)SrcTy;
   assert(SrcTy != IceType_i64);
 
   if (MovInstr->isMultiDest() || MovInstr->isMultiSource())
     return;
 
   bool Legalized = false;
+  auto *SrcR = llvm::cast<Variable>(Src);
+  if (Dest->hasReg() && SrcR->hasReg()) {
+    // This might be a GP to/from FP move generated due to argument passing.
+    // Use mtc1/mfc1 instead of mov.[s/d] if src and dst registers are of
+    // different types.
+    const bool IsDstGPR = RegMIPS32::isGPRReg(Dest->getRegNum());
+    const bool IsSrcGPR = RegMIPS32::isGPRReg(SrcR->getRegNum());
+    const RegNumT SRegNum = SrcR->getRegNum();
+    const RegNumT DRegNum = Dest->getRegNum();
+    if (IsDstGPR != IsSrcGPR) {
+      if (IsDstGPR) {
+        // Dest is GPR and SrcR is FPR. Use mfc1.
+        if (typeWidthInBytes(Dest->getType()) == 8) {
+          // Split it into two mfc1 instructions
+          Variable *SrcGPRHi = Target->makeReg(
+              IceType_f32, RegMIPS32::get64PairFirstRegNum(SRegNum));
+          Variable *SrcGPRLo = Target->makeReg(
+              IceType_f32, RegMIPS32::get64PairSecondRegNum(SRegNum));
+          Variable *DstFPRHi = Target->makeReg(
+              IceType_i32, RegMIPS32::get64PairFirstRegNum(DRegNum));
+          Variable *DstFPRLo = Target->makeReg(
+              IceType_i32, RegMIPS32::get64PairSecondRegNum(DRegNum));
+          Target->_mov(DstFPRHi, SrcGPRLo);
+          Target->_mov(DstFPRLo, SrcGPRHi);
+          Legalized = true;
+        } else {
+          Variable *SrcGPR = Target->makeReg(IceType_f32, SRegNum);
+          Variable *DstFPR = Target->makeReg(IceType_i32, DRegNum);
+          Target->_mov(DstFPR, SrcGPR);
+          Legalized = true;
+        }
+      } else {
+        // Dest is FPR and SrcR is GPR. Use mtc1.
+        if (typeWidthInBytes(SrcR->getType()) == 8) {
+          // Split it into two mtc1 instructions
+          Variable *SrcGPRHi = Target->makeReg(
+              IceType_i32, RegMIPS32::get64PairFirstRegNum(SRegNum));
+          Variable *SrcGPRLo = Target->makeReg(
+              IceType_i32, RegMIPS32::get64PairSecondRegNum(SRegNum));
+          Variable *DstFPRHi = Target->makeReg(
+              IceType_f32, RegMIPS32::get64PairFirstRegNum(DRegNum));
+          Variable *DstFPRLo = Target->makeReg(
+              IceType_f32, RegMIPS32::get64PairSecondRegNum(DRegNum));
+          Target->_mov(DstFPRHi, SrcGPRLo);
+          Target->_mov(DstFPRLo, SrcGPRHi);
+          Legalized = true;
+        } else {
+          Variable *SrcGPR = Target->makeReg(IceType_i32, SRegNum);
+          Variable *DstFPR = Target->makeReg(IceType_f32, DRegNum);
+          Target->_mov(DstFPR, SrcGPR);
+          Legalized = true;
+        }
+      }
+    }
+    if (Legalized) {
+      if (MovInstr->isDestRedefined()) {
+        Target->_set_dest_redefined();
+      }
+      MovInstr->setDeleted();
+      return;
+    }
+  }
+
   if (!Dest->hasReg()) {
     auto *SrcR = llvm::cast<Variable>(Src);
     assert(SrcR->hasReg());
     assert(!SrcR->isRematerializable());
     const int32_t Offset = Dest->getStackOffset();
 
     // This is a _mov(Mem(), Variable), i.e., a store.
     auto *Base = Target->getPhysicalRegister(Target->getFrameOrStackReg());
 
     OperandMIPS32Mem *Addr = OperandMIPS32Mem::create(
         Target->Func, DestTy, Base,
         llvm::cast<ConstantInteger32>(Target->Ctx->getConstantInt32(Offset)));
 
     // FP arguments are passed in GP reg if first argument is in GP. In this
     // case type of the SrcR is still FP thus we need to explicitly generate sw
     // instead of swc1.
     const RegNumT RegNum = SrcR->getRegNum();
-    const bool isSrcGPReg = ((unsigned)RegNum >= RegMIPS32::Reg_A0 &&
-                             (unsigned)RegNum <= RegMIPS32::Reg_A3) ||
-                            ((unsigned)RegNum >= RegMIPS32::Reg_A0A1 &&
-                             (unsigned)RegNum <= RegMIPS32::Reg_A2A3);
-    if (SrcTy == IceType_f32 && isSrcGPReg == true) {
+    const bool IsSrcGPReg = RegMIPS32::isGPRReg(SrcR->getRegNum());
+    if (SrcTy == IceType_f32 && IsSrcGPReg == true) {
       Variable *SrcGPR = Target->makeReg(IceType_i32, RegNum);
       Target->_sw(SrcGPR, Addr);
-    } else if (SrcTy == IceType_f64 && isSrcGPReg == true) {
-      Variable *SrcGPRHi, *SrcGPRLo;
-      if (RegNum == RegMIPS32::Reg_A0A1) {
-        SrcGPRLo = Target->makeReg(IceType_i32, RegMIPS32::Reg_A0);
-        SrcGPRHi = Target->makeReg(IceType_i32, RegMIPS32::Reg_A1);
-      } else {
-        SrcGPRLo = Target->makeReg(IceType_i32, RegMIPS32::Reg_A2);
-        SrcGPRHi = Target->makeReg(IceType_i32, RegMIPS32::Reg_A3);
-      }
+    } else if (SrcTy == IceType_f64 && IsSrcGPReg == true) {
+      Variable *SrcGPRHi =
+          Target->makeReg(IceType_i32, RegMIPS32::get64PairFirstRegNum(RegNum));
+      Variable *SrcGPRLo = Target->makeReg(
+          IceType_i32, RegMIPS32::get64PairSecondRegNum(RegNum));
       OperandMIPS32Mem *AddrHi = OperandMIPS32Mem::create(
           Target->Func, DestTy, Base,
           llvm::cast<ConstantInteger32>(
               Target->Ctx->getConstantInt32(Offset + 4)));
       Target->_sw(SrcGPRLo, Addr);
       Target->_sw(SrcGPRHi, AddrHi);
     } else {
       Target->_sw(SrcR, Addr);
     }
 
@@ skipping 897 matching lines @@
   }
   case InstCast::Fptrunc:
     // Use _cvt_d_s
     UnimplementedLoweringError(this, Instr);
     break;
   case InstCast::Fpext: {
     // Use _cvt_s_d
     UnimplementedLoweringError(this, Instr);
     break;
   }
-  case InstCast::Fptosi:
-    UnimplementedLoweringError(this, Instr);
+  case InstCast::Fptosi: {

[obucinac, 2016/09/13 17:49:01]

Fptosi cast is covered by genTargetHelperCallSFor.

[jaydeep.patil, 2016/09/14 04:42:44]

Done.

+    if (Src0Ty == IceType_f32 && DestTy == IceType_i32) {
+      Variable *Src0R = legalizeToReg(Src0);
+      Variable *FTmp = makeReg(IceType_f32);
+      _trunc_w_s(FTmp, Src0R);
+      _mov(Dest, FTmp);
+    } else {
+      UnimplementedLoweringError(this, Instr);
+    }
     break;
+  }
   case InstCast::Fptoui:
     UnimplementedLoweringError(this, Instr);
     break;
-  case InstCast::Sitofp:
-    UnimplementedLoweringError(this, Instr);
+  case InstCast::Sitofp: {

[obucinac, 2016/09/13 17:49:01]

Sitofp cast is covered by genTargetHelperCallSFor.

[jaydeep.patil, 2016/09/14 04:42:44]

Done.

+    if (Src0Ty == IceType_i32 && DestTy == IceType_f32) {
+      Variable *Src0R = legalizeToReg(Src0);
+      Variable *FTmp1 = makeReg(IceType_f32);
+      Variable *FTmp2 = makeReg(IceType_f32);
+      _mov(FTmp1, Src0R);
+      _cvt_s_w(FTmp2, FTmp1);
+      _mov(Dest, FTmp2);
+    } else {
+      UnimplementedLoweringError(this, Instr);
+    }
     break;
+  }
   case InstCast::Uitofp: {
     UnimplementedLoweringError(this, Instr);
     break;
   }
   case InstCast::Bitcast: {
     UnimplementedLoweringError(this, Instr);
     break;
   }
   }
 }
@@ skipping 680 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice