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Side by Side Diff: src/arm/macro-assembler-arm.cc

Issue 2314003003: Revert of [turbofan] ARM: Implement vswp and use in gap resolver (Closed)
Patch Set: Created 4 years, 3 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> // For LONG_MIN, LONG_MAX. 5 #include <limits.h> // For LONG_MIN, LONG_MAX.
6 6
7 #if V8_TARGET_ARCH_ARM 7 #if V8_TARGET_ARCH_ARM
8 8
9 #include "src/base/bits.h" 9 #include "src/base/bits.h"
10 #include "src/base/division-by-constant.h" 10 #include "src/base/division-by-constant.h"
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1047 1047
1048 1048
1049 void MacroAssembler::VmovLow(DwVfpRegister dst, Register src) { 1049 void MacroAssembler::VmovLow(DwVfpRegister dst, Register src) {
1050 if (dst.code() < 16) { 1050 if (dst.code() < 16) {
1051 const LowDwVfpRegister loc = LowDwVfpRegister::from_code(dst.code()); 1051 const LowDwVfpRegister loc = LowDwVfpRegister::from_code(dst.code());
1052 vmov(loc.low(), src); 1052 vmov(loc.low(), src);
1053 } else { 1053 } else {
1054 vmov(dst, VmovIndexLo, src); 1054 vmov(dst, VmovIndexLo, src);
1055 } 1055 }
1056 } 1056 }
1057
1058 void MacroAssembler::LslPair(Register dst_low, Register dst_high, 1057 void MacroAssembler::LslPair(Register dst_low, Register dst_high,
1059 Register src_low, Register src_high, 1058 Register src_low, Register src_high,
1060 Register scratch, Register shift) { 1059 Register scratch, Register shift) {
1061 DCHECK(!AreAliased(dst_high, src_low)); 1060 DCHECK(!AreAliased(dst_high, src_low));
1062 DCHECK(!AreAliased(dst_high, shift)); 1061 DCHECK(!AreAliased(dst_high, shift));
1063 1062
1064 Label less_than_32; 1063 Label less_than_32;
1065 Label done; 1064 Label done;
1066 rsb(scratch, shift, Operand(32), SetCC); 1065 rsb(scratch, shift, Operand(32), SetCC);
1067 b(gt, &less_than_32); 1066 b(gt, &less_than_32);
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4167 } 4166 }
4168 } 4167 }
4169 if (mag.shift > 0) mov(result, Operand(result, ASR, mag.shift)); 4168 if (mag.shift > 0) mov(result, Operand(result, ASR, mag.shift));
4170 add(result, result, Operand(dividend, LSR, 31)); 4169 add(result, result, Operand(dividend, LSR, 31));
4171 } 4170 }
4172 4171
4173 } // namespace internal 4172 } // namespace internal
4174 } // namespace v8 4173 } // namespace v8
4175 4174
4176 #endif // V8_TARGET_ARCH_ARM 4175 #endif // V8_TARGET_ARCH_ARM
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