Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(796)

Side by Side Diff: src/arm/simulator-arm.cc

Issue 2313803003: [turbofan] ARM: Implement vswp and use in gap resolver (Closed)
Patch Set: Fix git's broken rebase Created 4 years, 3 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/arm/macro-assembler-arm.cc ('k') | src/compiler/arm/code-generator-arm.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <stdarg.h> 5 #include <stdarg.h>
6 #include <stdlib.h> 6 #include <stdlib.h>
7 #include <cmath> 7 #include <cmath>
8 8
9 #if V8_TARGET_ARCH_ARM 9 #if V8_TARGET_ARCH_ARM
10 10
(...skipping 3765 matching lines...) Expand 10 before | Expand all | Expand 10 after
3776 int elements = 64 / esize; 3776 int elements = 64 / esize;
3777 uint8_t from[8]; 3777 uint8_t from[8];
3778 get_d_register(Vm, reinterpret_cast<uint64_t*>(from)); 3778 get_d_register(Vm, reinterpret_cast<uint64_t*>(from));
3779 uint16_t to[8]; 3779 uint16_t to[8];
3780 int e = 0; 3780 int e = 0;
3781 while (e < elements) { 3781 while (e < elements) {
3782 to[e] = from[e]; 3782 to[e] = from[e];
3783 e++; 3783 e++;
3784 } 3784 }
3785 set_q_register(Vd, reinterpret_cast<uint64_t*>(to)); 3785 set_q_register(Vd, reinterpret_cast<uint64_t*>(to));
3786 } else if ((instr->Bits(21, 16) == 0x32) && (instr->Bits(11, 7) == 0) &&
3787 (instr->Bit(4) == 0)) {
3788 int vd = instr->VFPDRegValue(kDoublePrecision);
3789 int vm = instr->VFPMRegValue(kDoublePrecision);
3790 if (instr->Bit(6) == 0) {
3791 // vswp Dd, Dm.
3792 uint64_t dval, mval;
3793 get_d_register(vd, &dval);
3794 get_d_register(vm, &mval);
3795 set_d_register(vm, &dval);
3796 set_d_register(vd, &mval);
3797 } else {
3798 // Q register vswp unimplemented.
3799 UNIMPLEMENTED();
3800 }
3786 } else { 3801 } else {
3787 UNIMPLEMENTED(); 3802 UNIMPLEMENTED();
3788 } 3803 }
3789 break; 3804 break;
3790 case 8: 3805 case 8:
3791 if (instr->Bits(21, 20) == 0) { 3806 if (instr->Bits(21, 20) == 0) {
3792 // vst1 3807 // vst1
3793 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); 3808 int Vd = (instr->Bit(22) << 4) | instr->VdValue();
3794 int Rn = instr->VnValue(); 3809 int Rn = instr->VnValue();
3795 int type = instr->Bits(11, 8); 3810 int type = instr->Bits(11, 8);
(...skipping 500 matching lines...) Expand 10 before | Expand all | Expand 10 after
4296 set_register(sp, current_sp + sizeof(uintptr_t)); 4311 set_register(sp, current_sp + sizeof(uintptr_t));
4297 return address; 4312 return address;
4298 } 4313 }
4299 4314
4300 } // namespace internal 4315 } // namespace internal
4301 } // namespace v8 4316 } // namespace v8
4302 4317
4303 #endif // USE_SIMULATOR 4318 #endif // USE_SIMULATOR
4304 4319
4305 #endif // V8_TARGET_ARCH_ARM 4320 #endif // V8_TARGET_ARCH_ARM
OLDNEW
« no previous file with comments | « src/arm/macro-assembler-arm.cc ('k') | src/compiler/arm/code-generator-arm.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698