Adds logical operations to arm64.

runtime/vm/disassembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 #include "platform/assert.h"
 
@@ skipping 329 matching lines @@
                                    "lsl %d",
                                    shift);
       }
       return 2;
     }
     case 'm': {
       ASSERT(STRING_STARTS_WITH(format, "memop"));
       PrintMemOperand(instr);
       return 5;
     }
+    case 'b': {
+      ASSERT(STRING_STARTS_WITH(format, "bitimm"));
+      const uint64_t imm = instr->ImmLogical();
+      buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                 remaining_size_in_buffer(),
+                                 "0x%"Px64,
+                                 imm);
+      return 6;
+    }
     default: {
       UNREACHABLE();
       break;
     }
   }
   UNREACHABLE();
   return -1;
 }
 
 
@@ skipping 47 matching lines @@
   if (instr->Bit(22) == 1) {
     Format(instr, "ldr'sz 'rt, 'memop");
   } else {
     Format(instr, "str'sz 'rt, 'memop");
   }
 }
 
 
 void ARM64Decoder::DecodeAddSubImm(Instr* instr) {
   switch (instr->Bit(30)) {
+    case 0: {
+      if ((instr->RdField() == R31) && (instr->SFField())) {
+        Format(instr, "cmni'sf 'rn, 'imm12s");
+      } else {
+        Format(instr, "addi'sf's 'rd, 'rn, 'imm12s");
+      }
+      break;
+    }
+    case 1: {
+      if ((instr->RdField() == R31) && (instr->SFField())) {
+        Format(instr, "cmpi'sf 'rn, 'imm12s");
+      } else {
+        Format(instr, "subi'sf's 'rd, 'rn, 'imm12s");
+      }
+      break;
+    }
+    default:
+      Unknown(instr);
+      break;
+  }
+}
+
+
+void ARM64Decoder::DecodeLogicalImm(Instr* instr) {
+  int op = instr->Bits(29, 2);
+  switch (op) {
     case 0:
-      Format(instr, "addi'sf's 'rd, 'rn, 'imm12s");
+      Format(instr, "andi'sf 'rd, 'rn, 'bitimm");
       break;
     case 1:
-      Format(instr, "subi'sf's 'rd, 'rn, 'imm12s");
+      Format(instr, "orri'sf 'rd, 'rn, 'bitimm");
+      break;
+    case 2:
+      Format(instr, "eori'sf 'rd, 'rn, 'bitimm");
+      break;
+    case 3:
+      Format(instr, "andi'sfs 'rd, 'rn, 'bitimm");
       break;
     default:
       Unknown(instr);
       break;
   }
 }
 
+
 void ARM64Decoder::DecodeDPImmediate(Instr* instr) {
   if (instr->IsMoveWideOp()) {
     DecodeMoveWide(instr);
   } else if (instr->IsAddSubImmOp()) {
     DecodeAddSubImm(instr);
+  } else if (instr->IsLogicalImmOp()) {
+    DecodeLogicalImm(instr);
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeExceptionGen(Instr* instr) {
   if ((instr->Bits(0, 2) == 1) && (instr->Bits(2, 3) == 0) &&
       (instr->Bits(21, 3) == 0)) {
     Format(instr, "svc 'imm16");
@@ skipping 60 matching lines @@
   if (instr->IsLoadStoreRegOp()) {
     DecodeLoadStoreReg(instr);
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeAddSubShiftExt(Instr* instr) {
   switch (instr->Bit(30)) {
+    case 0: {
+      if ((instr->RdField() == R31) && (instr->SFField())) {
+        Format(instr, "cmn'sf 'rn, 'shift_op");
+      } else {
+        Format(instr, "add'sf's 'rd, 'rn, 'shift_op");
+      }
+      break;
+    }
+    case 1: {
+      if ((instr->RdField() == R31) && (instr->SFField())) {
+        Format(instr, "cmp'sf 'rn, 'shift_op");
+      } else {
+        Format(instr, "sub'sf's 'rd, 'rn, 'shift_op");
+      }
+      break;
+    }
+    default:
+      UNREACHABLE();
+      break;
+  }
+}
+
+
+void ARM64Decoder::DecodeLogicalShift(Instr* instr) {
+  const int op = (instr->Bits(29, 2) << 1) | instr->Bit(21);
+  switch (op) {
     case 0:
-      Format(instr, "add'sf's 'rd, 'rn, 'shift_op");
+      Format(instr, "and'sf 'rd, 'rn, 'shift_op");
       break;
     case 1:
-      Format(instr, "sub'sf's 'rd, 'rn, 'shift_op");
+      Format(instr, "bic'sf 'rd, 'rn, 'shift_op");
+      break;
+    case 2:
+      Format(instr, "orr'sf 'rd, 'rn, 'shift_op");
+      break;
+    case 3:
+      Format(instr, "orn'sf 'rd, 'rn, 'shift_op");
+      break;
+    case 4:
+      Format(instr, "eor'sf 'rd, 'rn, 'shift_op");
+      break;
+    case 5:
+      Format(instr, "eon'sf 'rd, 'rn, 'shift_op");
+      break;
+    case 6:
+      Format(instr, "and'sfs 'rd, 'rn, 'shift_op");
+      break;
+    case 7:
+      Format(instr, "bic'sfs 'rd, 'rn, 'shift_op");
       break;
     default:
       UNREACHABLE();
       break;
   }
 }
 
 
 void ARM64Decoder::DecodeDPRegister(Instr* instr) {
   if (instr->IsAddSubShiftExtOp()) {
     DecodeAddSubShiftExt(instr);
+  } else if (instr->IsLogicalShiftOp()) {
+    DecodeLogicalShift(instr);
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeDPSimd1(Instr* instr) {
   Unknown(instr);
 }
 
@@ skipping 64 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM