MIPS: Implement MADD.S, MSUB, MADDF and MSUBF.

src/mips64/simulator-mips64.cc

Index: src/mips64/simulator-mips64.cc
diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc
index 780c90c16b5ef87a3e3a8c92664267482cd25a02..662b873965d4d9bc5294d0cce33e8f6c0d8cb217 100644
--- a/src/mips64/simulator-mips64.cc
+++ b/src/mips64/simulator-mips64.cc
@@ -2421,6 +2421,14 @@ void Simulator::DecodeTypeRegisterSRsType() {
     case SUB_S:
       set_fpu_register_float(fd_reg(), fs - ft);
       break;
+    case MADDF_S:
+      DCHECK(kArchVariant == kMips64r6);
+      set_fpu_register_float(fd_reg(), fd + (fs * ft));
+      break;
+    case MSUBF_S:
+      DCHECK(kArchVariant == kMips64r6);
+      set_fpu_register_float(fd_reg(), fd - (fs * ft));
+      break;
     case MUL_S:
       set_fpu_register_float(fd_reg(), fs * ft);
       break;
@@ -2824,6 +2832,14 @@ void Simulator::DecodeTypeRegisterDRsType() {
     case SUB_D:
       set_fpu_register_double(fd_reg(), fs - ft);
       break;
+    case MADDF_D:
+      DCHECK(kArchVariant == kMips64r6);
+      set_fpu_register_double(fd_reg(), fd + (fs * ft));
+      break;
+    case MSUBF_D:
+      DCHECK(kArchVariant == kMips64r6);
+      set_fpu_register_double(fd_reg(), fd - (fs * ft));
+      break;
     case MUL_D:
       set_fpu_register_double(fd_reg(), fs * ft);
       break;
@@ -3305,13 +3321,42 @@ void Simulator::DecodeTypeRegisterCOP1() {
 
 void Simulator::DecodeTypeRegisterCOP1X() {

[balazs.kilvady, 2016/09/05 12:54:00]

Since fr, fs and ft is used in all switch cases, please declare and initialize
them at van place before the switch.

[Ilija.Pavlovic1, 2016/09/07 08:44:29]

These variables are declared as "float" and in MADD_D and MSUB_D are declared as
"double". Therefore these declarations must be on this places.

[balazs.kilvady, 2016/09/07 09:46:52]

Acknowledged.

   switch (get_instr()->FunctionFieldRaw()) {
-    case MADD_D:
+    case MADD_S: {
+      DCHECK(kArchVariant == kMips64r2);
+      float fr, ft, fs;
+      fr = get_fpu_register_float(fr_reg());
+      fs = get_fpu_register_float(fs_reg());
+      ft = get_fpu_register_float(ft_reg());
+      set_fpu_register_float(fd_reg(), fs * ft + fr);
+      break;
+    }
+    case MSUB_S: {
+      DCHECK(kArchVariant == kMips64r2);
+      float fr, ft, fs;
+      fr = get_fpu_register_float(fr_reg());
+      fs = get_fpu_register_float(fs_reg());
+      ft = get_fpu_register_float(ft_reg());
+      set_fpu_register_float(fd_reg(), fs * ft - fr);
+      break;
+    }
+    case MADD_D: {
+      DCHECK(kArchVariant == kMips64r2);
       double fr, ft, fs;
       fr = get_fpu_register_double(fr_reg());
       fs = get_fpu_register_double(fs_reg());
       ft = get_fpu_register_double(ft_reg());
       set_fpu_register_double(fd_reg(), fs * ft + fr);
       break;
+    }
+    case MSUB_D: {
+      DCHECK(kArchVariant == kMips64r2);
+      double fr, ft, fs;
+      fr = get_fpu_register_double(fr_reg());
+      fs = get_fpu_register_double(fs_reg());
+      ft = get_fpu_register_double(ft_reg());
+      set_fpu_register_double(fd_reg(), fs * ft - fr);
+      break;
+    }
     default:
       UNREACHABLE();
   }