MIPS: Implement MADD.S, MSUB, MADDF and MSUBF.

test/cctest/test-disasm-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
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 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
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@@ skipping 1072 matching lines @@
 
 
 TEST(ctc1_cfc1_disasm) {
   SET_UP();
   COMPARE(abs_d(f10, f31), "4620fa85       abs.d   f10, f31");
   COMPARE(ceil_w_s(f8, f31), "4600fa0e       ceil.w.s f8, f31");
   COMPARE(ctc1(a0, FCSR), "44c4f800       ctc1    a0, FCSR");
   COMPARE(cfc1(a0, FCSR), "4444f800       cfc1    a0, FCSR");
   VERIFY_RUN();
 }
+
+TEST(madd_msub_maddf_msubf) {
+  SET_UP();
+  if (IsMipsArchVariant(kMips32r2)) {
+    COMPARE(madd_s(f4, f6, f8, f10), "4cca4120       madd.s  f4, f6, f8, f10");
+    COMPARE(madd_d(f4, f6, f8, f10), "4cca4121       madd.d  f4, f6, f8, f10");
+    COMPARE(msub_s(f4, f6, f8, f10), "4cca4128       msub.s  f4, f6, f8, f10");
+    COMPARE(msub_d(f4, f6, f8, f10), "4cca4129       msub.d  f4, f6, f8, f10");
+  }
+  if (IsMipsArchVariant(kMips32r6)) {
+    COMPARE(maddf_s(f4, f8, f10), "460a4118       maddf.s  f4, f8, f10");
+    COMPARE(maddf_d(f4, f8, f10), "462a4118       maddf.d  f4, f8, f10");
+    COMPARE(msubf_s(f4, f8, f10), "460a4119       msubf.s  f4, f8, f10");
+    COMPARE(msubf_d(f4, f8, f10), "462a4119       msubf.d  f4, f8, f10");
+  }
+  VERIFY_RUN();
+}