MIPS: Implement MADD.S, MSUB, MADDF and MSUBF.

src/mips64/simulator-mips64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_MIPS64
@@ skipping 2403 matching lines @@
         set_fcsr_bit(kFCSRInexactFlagBit, true);
       }
       break;
     }
     case ADD_S:
       set_fpu_register_float(fd_reg(), fs + ft);
       break;
     case SUB_S:
       set_fpu_register_float(fd_reg(), fs - ft);
       break;
+    case MADDF_S:
+      DCHECK(kArchVariant == kMips64r6);
+      set_fpu_register_float(fd_reg(), fd + (fs * ft));
+      break;
+    case MSUBF_S:
+      DCHECK(kArchVariant == kMips64r6);
+      set_fpu_register_float(fd_reg(), fd - (fs * ft));
+      break;
     case MUL_S:
       set_fpu_register_float(fd_reg(), fs * ft);
       break;
     case DIV_S:
       set_fpu_register_float(fd_reg(), fs / ft);
       break;
     case ABS_S:
       set_fpu_register_float(fd_reg(), fabs(fs));
       break;
     case MOV_S:
@@ skipping 383 matching lines @@
     case MAX:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), FPUMax(ft, fs));
       break;
     case ADD_D:
       set_fpu_register_double(fd_reg(), fs + ft);
       break;
     case SUB_D:
       set_fpu_register_double(fd_reg(), fs - ft);
       break;
+    case MADDF_D:
+      DCHECK(kArchVariant == kMips64r6);
+      set_fpu_register_double(fd_reg(), fd + (fs * ft));
+      break;
+    case MSUBF_D:
+      DCHECK(kArchVariant == kMips64r6);
+      set_fpu_register_double(fd_reg(), fd - (fs * ft));
+      break;
     case MUL_D:
       set_fpu_register_double(fd_reg(), fs * ft);
       break;
     case DIV_D:
       set_fpu_register_double(fd_reg(), fs / ft);
       break;
     case ABS_D:
       set_fpu_register_double(fd_reg(), fabs(fs));
       break;
     case MOV_D:
@@ skipping 461 matching lines @@
       DecodeTypeRegisterLRsType();
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterCOP1X() {
   switch (get_instr()->FunctionFieldRaw()) {
-    case MADD_D:
+    case MADD_S: {
+      DCHECK(kArchVariant == kMips64r2);
+      float fr, ft, fs;
+      fr = get_fpu_register_float(fr_reg());
+      fs = get_fpu_register_float(fs_reg());
+      ft = get_fpu_register_float(ft_reg());
+      set_fpu_register_float(fd_reg(), fs * ft + fr);
+      break;
+    }
+    case MSUB_S: {
+      DCHECK(kArchVariant == kMips64r2);
+      float fr, ft, fs;
+      fr = get_fpu_register_float(fr_reg());
+      fs = get_fpu_register_float(fs_reg());
+      ft = get_fpu_register_float(ft_reg());
+      set_fpu_register_float(fd_reg(), fs * ft - fr);
+      break;
+    }
+    case MADD_D: {
+      DCHECK(kArchVariant == kMips64r2);
       double fr, ft, fs;
       fr = get_fpu_register_double(fr_reg());
       fs = get_fpu_register_double(fs_reg());
       ft = get_fpu_register_double(ft_reg());
       set_fpu_register_double(fd_reg(), fs * ft + fr);
       break;
+    }
+    case MSUB_D: {
+      DCHECK(kArchVariant == kMips64r2);
+      double fr, ft, fs;
+      fr = get_fpu_register_double(fr_reg());
+      fs = get_fpu_register_double(fs_reg());
+      ft = get_fpu_register_double(ft_reg());
+      set_fpu_register_double(fd_reg(), fs * ft - fr);
+      break;
+    }
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterSPECIAL() {
   int64_t i64hilo;
   uint64_t u64hilo;
   int64_t alu_out;
@@ skipping 1608 matching lines @@
 }
 
 
 #undef UNSUPPORTED
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS64