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Side by Side Diff: src/mips/simulator-mips.cc

Issue 2313623002: MIPS: Implement MADD.S, MSUB, MADDF and MSUBF. (Closed)
Patch Set: Added blocks and unreachable sections. Created 4 years, 3 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS 10 #if V8_TARGET_ARCH_MIPS
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2475 case MAXA: 2475 case MAXA:
2476 DCHECK(IsMipsArchVariant(kMips32r6)); 2476 DCHECK(IsMipsArchVariant(kMips32r6));
2477 set_fpu_register_double(fd_reg(), FPUMaxA(ft, fs)); 2477 set_fpu_register_double(fd_reg(), FPUMaxA(ft, fs));
2478 break; 2478 break;
2479 case ADD_D: 2479 case ADD_D:
2480 set_fpu_register_double(fd_reg(), fs + ft); 2480 set_fpu_register_double(fd_reg(), fs + ft);
2481 break; 2481 break;
2482 case SUB_D: 2482 case SUB_D:
2483 set_fpu_register_double(fd_reg(), fs - ft); 2483 set_fpu_register_double(fd_reg(), fs - ft);
2484 break; 2484 break;
2485 case MADDF_D:
2486 DCHECK(IsMipsArchVariant(kMips32r6));
2487 set_fpu_register_double(fd_reg(), fd + (fs * ft));
2488 break;
2489 case MSUBF_D:
2490 DCHECK(IsMipsArchVariant(kMips32r6));
2491 set_fpu_register_double(fd_reg(), fd - (fs * ft));
2492 break;
2485 case MUL_D: 2493 case MUL_D:
2486 set_fpu_register_double(fd_reg(), fs * ft); 2494 set_fpu_register_double(fd_reg(), fs * ft);
2487 break; 2495 break;
2488 case DIV_D: 2496 case DIV_D:
2489 set_fpu_register_double(fd_reg(), fs / ft); 2497 set_fpu_register_double(fd_reg(), fs / ft);
2490 break; 2498 break;
2491 case ABS_D: 2499 case ABS_D:
2492 set_fpu_register_double(fd_reg(), fabs(fs)); 2500 set_fpu_register_double(fd_reg(), fabs(fs));
2493 break; 2501 break;
2494 case MOV_D: 2502 case MOV_D:
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2880 set_fcsr_bit(kFCSRInexactFlagBit, true); 2888 set_fcsr_bit(kFCSRInexactFlagBit, true);
2881 } 2889 }
2882 break; 2890 break;
2883 } 2891 }
2884 case ADD_S: 2892 case ADD_S:
2885 set_fpu_register_float(fd_reg(), fs + ft); 2893 set_fpu_register_float(fd_reg(), fs + ft);
2886 break; 2894 break;
2887 case SUB_S: 2895 case SUB_S:
2888 set_fpu_register_float(fd_reg(), fs - ft); 2896 set_fpu_register_float(fd_reg(), fs - ft);
2889 break; 2897 break;
2898 case MADDF_S:
2899 DCHECK(IsMipsArchVariant(kMips32r6));
2900 set_fpu_register_float(fd_reg(), fd + (fs * ft));
2901 break;
2902 case MSUBF_S:
2903 DCHECK(IsMipsArchVariant(kMips32r6));
2904 set_fpu_register_float(fd_reg(), fd - (fs * ft));
2905 break;
2890 case MUL_S: 2906 case MUL_S:
2891 set_fpu_register_float(fd_reg(), fs * ft); 2907 set_fpu_register_float(fd_reg(), fs * ft);
2892 break; 2908 break;
2893 case DIV_S: 2909 case DIV_S:
2894 set_fpu_register_float(fd_reg(), fs / ft); 2910 set_fpu_register_float(fd_reg(), fs / ft);
2895 break; 2911 break;
2896 case ABS_S: 2912 case ABS_S:
2897 set_fpu_register_float(fd_reg(), fabs(fs)); 2913 set_fpu_register_float(fd_reg(), fabs(fs));
2898 break; 2914 break;
2899 case MOV_S: 2915 case MOV_S:
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3368 // Not implemented. 3384 // Not implemented.
3369 UNREACHABLE(); 3385 UNREACHABLE();
3370 default: 3386 default:
3371 UNREACHABLE(); 3387 UNREACHABLE();
3372 } 3388 }
3373 } 3389 }
3374 3390
3375 3391
3376 void Simulator::DecodeTypeRegisterCOP1X() { 3392 void Simulator::DecodeTypeRegisterCOP1X() {
3377 switch (get_instr()->FunctionFieldRaw()) { 3393 switch (get_instr()->FunctionFieldRaw()) {
3378 case MADD_D: 3394 case MADD_S: {
3395 DCHECK(IsMipsArchVariant(kMips32r2));
3396 float fr, ft, fs;
3397 fr = get_fpu_register_float(fr_reg());
3398 fs = get_fpu_register_float(fs_reg());
3399 ft = get_fpu_register_float(ft_reg());
3400 set_fpu_register_float(fd_reg(), fs * ft + fr);
3401 break;
3402 }
3403 case MSUB_S: {
3404 DCHECK(IsMipsArchVariant(kMips32r2));
3405 float fr, ft, fs;
3406 fr = get_fpu_register_float(fr_reg());
3407 fs = get_fpu_register_float(fs_reg());
3408 ft = get_fpu_register_float(ft_reg());
3409 set_fpu_register_float(fd_reg(), fs * ft - fr);
3410 break;
3411 }
3412 case MADD_D: {
3413 DCHECK(IsMipsArchVariant(kMips32r2));
3379 double fr, ft, fs; 3414 double fr, ft, fs;
3380 fr = get_fpu_register_double(fr_reg()); 3415 fr = get_fpu_register_double(fr_reg());
3381 fs = get_fpu_register_double(fs_reg()); 3416 fs = get_fpu_register_double(fs_reg());
3382 ft = get_fpu_register_double(ft_reg()); 3417 ft = get_fpu_register_double(ft_reg());
3383 set_fpu_register_double(fd_reg(), fs * ft + fr); 3418 set_fpu_register_double(fd_reg(), fs * ft + fr);
3384 break; 3419 break;
3420 }
3421 case MSUB_D: {
3422 DCHECK(IsMipsArchVariant(kMips32r2));
3423 double fr, ft, fs;
3424 fr = get_fpu_register_double(fr_reg());
3425 fs = get_fpu_register_double(fs_reg());
3426 ft = get_fpu_register_double(ft_reg());
3427 set_fpu_register_double(fd_reg(), fs * ft - fr);
3428 break;
3429 }
3385 default: 3430 default:
3386 UNREACHABLE(); 3431 UNREACHABLE();
3387 } 3432 }
3388 } 3433 }
3389 3434
3390 3435
3391 void Simulator::DecodeTypeRegisterSPECIAL() { 3436 void Simulator::DecodeTypeRegisterSPECIAL() {
3392 int64_t alu_out = 0x12345678; 3437 int64_t alu_out = 0x12345678;
3393 int64_t i64hilo = 0; 3438 int64_t i64hilo = 0;
3394 uint64_t u64hilo = 0; 3439 uint64_t u64hilo = 0;
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4581 4626
4582 4627
4583 #undef UNSUPPORTED 4628 #undef UNSUPPORTED
4584 4629
4585 } // namespace internal 4630 } // namespace internal
4586 } // namespace v8 4631 } // namespace v8
4587 4632
4588 #endif // USE_SIMULATOR 4633 #endif // USE_SIMULATOR
4589 4634
4590 #endif // V8_TARGET_ARCH_MIPS 4635 #endif // V8_TARGET_ARCH_MIPS
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