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Issue 23112016: Drop unused rdtsc instruction. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 4 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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431 431
432 432
433 // Feature flags bit positions. They are mostly based on the CPUID spec. 433 // Feature flags bit positions. They are mostly based on the CPUID spec.
434 // (We assign CPUID itself to one of the currently reserved bits -- 434 // (We assign CPUID itself to one of the currently reserved bits --
435 // feel free to change this if needed.) 435 // feel free to change this if needed.)
436 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX. 436 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX.
437 enum CpuFeature { SSE4_1 = 32 + 19, // x86 437 enum CpuFeature { SSE4_1 = 32 + 19, // x86
438 SSE3 = 32 + 0, // x86 438 SSE3 = 32 + 0, // x86
439 SSE2 = 26, // x86 439 SSE2 = 26, // x86
440 CMOV = 15, // x86 440 CMOV = 15, // x86
441 RDTSC = 4, // x86
442 CPUID = 10, // x86 441 CPUID = 10, // x86
443 VFP3 = 1, // ARM 442 VFP3 = 1, // ARM
444 ARMv7 = 2, // ARM 443 ARMv7 = 2, // ARM
445 SUDIV = 3, // ARM 444 SUDIV = 3, // ARM
446 UNALIGNED_ACCESSES = 4, // ARM 445 UNALIGNED_ACCESSES = 4, // ARM
447 MOVW_MOVT_IMMEDIATE_LOADS = 5, // ARM 446 MOVW_MOVT_IMMEDIATE_LOADS = 5, // ARM
448 VFP32DREGS = 6, // ARM 447 VFP32DREGS = 6, // ARM
449 NEON = 7, // ARM 448 NEON = 7, // ARM
450 SAHF = 0, // x86 449 SAHF = 0, // x86
451 FPU = 1}; // MIPS 450 FPU = 1}; // MIPS
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581 580
582 enum ClearExceptionFlag { 581 enum ClearExceptionFlag {
583 KEEP_EXCEPTION, 582 KEEP_EXCEPTION,
584 CLEAR_EXCEPTION 583 CLEAR_EXCEPTION
585 }; 584 };
586 585
587 586
588 } } // namespace v8::internal 587 } } // namespace v8::internal
589 588
590 #endif // V8_V8GLOBALS_H_ 589 #endif // V8_V8GLOBALS_H_
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