MIPS: Fix bug that prevents JALR to JAL optimizations.

src/mips/assembler-mips.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 2185 matching lines @@
   // 256 MB page. Note that with the jal/j instructions, we do not need to
   // load the register, but that code is left, since it makes it easy to
   // revert this process. A further optimization could try replacing the
   // li sequence with nops.
   // This optimization can only be applied if the rt-code from instr2 is the
   // register used for the jalr/jr. Finally, we have to skip 'jr ra', which is
   // mips return. Occasionally this lands after an li().
 
   Instr instr3 = instr_at(pc + 2 * kInstrSize);
   uint32_t ipc = reinterpret_cast<uint32_t>(pc + 3 * kInstrSize);
-  bool in_range = (ipc ^ static_cast<uint32_t>(itarget) >>
-                  (kImm26Bits + kImmFieldShift)) == 0;
+  bool in_range = ((ipc ^ itarget) >> (kImm26Bits + kImmFieldShift)) == 0;
   uint32_t target_field =
       static_cast<uint32_t>(itarget & kJumpAddrMask) >> kImmFieldShift;
   bool patched_jump = false;
 
 #ifndef ALLOW_JAL_IN_BOUNDARY_REGION
   // This is a workaround to the 24k core E156 bug (affect some 34k cores also).
   // Since the excluded space is only 64KB out of 256MB (0.02 %), we will just
   // apply this workaround for all cores so we don't have to identify the core.
   if (in_range) {
     // The 24k core E156 bug has some very specific requirements, we only check
@@ skipping 77 matching lines @@
   }
 
   if (patched) {
       CPU::FlushICache(pc+2, sizeof(Address));
   }
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS