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Side by Side Diff: tests_lit/llvm2ice_tests/load.ll

Issue 2301303003: [SubZero] Implement load and store for MIPS (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 3 months ago
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1 ; Simple test of the load instruction. 1 ; Simple test of the load instruction.
2 2
3 ; REQUIRES: allow_dump 3 ; REQUIRES: allow_dump
4 4
5 ; RUN: %p2i -i %s --args --verbose inst -threads=0 | FileCheck %s 5 ; RUN: %p2i -i %s --args --verbose inst -threads=0 | FileCheck %s
6 6
7 ; RUN: %if --need=target_MIPS32 --need=allow_dump \
8 ; RUN: --command %p2i --filetype=asm --assemble \
9 ; RUN: --disassemble --target mips32 -i %s --args -Om1 --skip-unimplemented \
10 ; RUN: -allow-externally-defined-symbols \
11 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \
12 ; RUN: --command FileCheck --check-prefix MIPS32 %s
13
7 define internal void @load_i64(i32 %addr_arg) { 14 define internal void @load_i64(i32 %addr_arg) {
8 entry: 15 entry:
9 %__1 = inttoptr i32 %addr_arg to i64* 16 %__1 = inttoptr i32 %addr_arg to i64*
10 %iv = load i64, i64* %__1, align 1 17 %iv = load i64, i64* %__1, align 1
11 ret void 18 ret void
12 19
13 ; CHECK: Initial CFG 20 ; CHECK: Initial CFG
14 ; CHECK: entry: 21 ; CHECK: entry:
15 ; CHECK-NEXT: %iv = load i64, i64* %addr_arg, align 1 22 ; CHECK-NEXT: %iv = load i64, i64* %addr_arg, align 1
16 ; CHECK-NEXT: ret void 23 ; CHECK-NEXT: ret void
17 } 24 }
18 25
26 ; MIPS32-LABEL: load_i64
27 ; MIPS32: lw {{.*}},0({{.*}})
28 ; MIPS32-NEXT: lw {{.*}},4({{.*}})
29
19 define internal void @load_i32(i32 %addr_arg) { 30 define internal void @load_i32(i32 %addr_arg) {
20 entry: 31 entry:
21 %__1 = inttoptr i32 %addr_arg to i32* 32 %__1 = inttoptr i32 %addr_arg to i32*
22 %iv = load i32, i32* %__1, align 1 33 %iv = load i32, i32* %__1, align 1
23 ret void 34 ret void
24 35
25 ; CHECK: Initial CFG 36 ; CHECK: Initial CFG
26 ; CHECK: entry: 37 ; CHECK: entry:
27 ; CHECK-NEXT: %iv = load i32, i32* %addr_arg, align 1 38 ; CHECK-NEXT: %iv = load i32, i32* %addr_arg, align 1
28 ; CHECK-NEXT: ret void 39 ; CHECK-NEXT: ret void
29 } 40 }
30 41
42 ; MIPS32-LABEL: load_i32
43 ; MIPS32: lw {{.*}},0({{.*}})
44
31 define internal void @load_i16(i32 %addr_arg) { 45 define internal void @load_i16(i32 %addr_arg) {
32 entry: 46 entry:
33 %__1 = inttoptr i32 %addr_arg to i16* 47 %__1 = inttoptr i32 %addr_arg to i16*
34 %iv = load i16, i16* %__1, align 1 48 %iv = load i16, i16* %__1, align 1
35 ret void 49 ret void
36 50
37 ; CHECK: Initial CFG 51 ; CHECK: Initial CFG
38 ; CHECK: entry: 52 ; CHECK: entry:
39 ; CHECK-NEXT: %iv = load i16, i16* %addr_arg, align 1 53 ; CHECK-NEXT: %iv = load i16, i16* %addr_arg, align 1
40 ; CHECK-NEXT: ret void 54 ; CHECK-NEXT: ret void
41 } 55 }
42 56
57 ; MIPS32-LABEL: load_i16
58 ; MIPS32: lh {{.*}},0({{.*}})
59
43 define internal void @load_i8(i32 %addr_arg) { 60 define internal void @load_i8(i32 %addr_arg) {
44 entry: 61 entry:
45 %__1 = inttoptr i32 %addr_arg to i8* 62 %__1 = inttoptr i32 %addr_arg to i8*
46 %iv = load i8, i8* %__1, align 1 63 %iv = load i8, i8* %__1, align 1
47 ret void 64 ret void
48 65
49 ; CHECK: Initial CFG 66 ; CHECK: Initial CFG
50 ; CHECK: entry: 67 ; CHECK: entry:
51 ; CHECK-NEXT: %iv = load i8, i8* %addr_arg, align 1 68 ; CHECK-NEXT: %iv = load i8, i8* %addr_arg, align 1
52 ; CHECK-NEXT: ret void 69 ; CHECK-NEXT: ret void
53 } 70 }
71
72 ; MIPS32-LABEL: load_i8
73 ; MIPS32: lb {{.*}},0({{.*}})
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