| Index: runtime/vm/intermediate_language_arm.cc
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| diff --git a/runtime/vm/intermediate_language_arm.cc b/runtime/vm/intermediate_language_arm.cc
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| index 04edbc16f79d8fdf060814c75a69fa3ae8a4d0ac..9cc159160cb70a5c19401711198c68441a94df81 100644
|
| --- a/runtime/vm/intermediate_language_arm.cc
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| +++ b/runtime/vm/intermediate_language_arm.cc
|
| @@ -3030,6 +3030,46 @@ void Float32x4ShuffleInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
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| }
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|
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|
| +LocationSummary* Simd32x4GetSignMaskInstr::MakeLocationSummary() const {
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| + const intptr_t kNumInputs = 1;
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| + const intptr_t kNumTemps = 1;
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| + LocationSummary* summary =
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| + new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
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| + summary->set_in(0, Location::FpuRegisterLocation(Q5));
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| + summary->set_temp(0, Location::RequiresRegister());
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| + summary->set_out(Location::RequiresRegister());
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| + return summary;
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| +}
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| +
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| +
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| +void Simd32x4GetSignMaskInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
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| + QRegister value = locs()->in(0).fpu_reg();
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| + DRegister dvalue0 = EvenDRegisterOf(value);
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| + DRegister dvalue1 = OddDRegisterOf(value);
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| +
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| + Register out = locs()->out().reg();
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| + Register temp = locs()->temp(0).reg();
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| +
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| + // X lane.
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| + __ vmovrs(out, EvenSRegisterOf(dvalue0));
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| + __ Lsr(out, out, 31);
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| + // Y lane.
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| + __ vmovrs(temp, OddSRegisterOf(dvalue0));
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| + __ Lsr(temp, temp, 31);
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| + __ orr(out, out, ShifterOperand(temp, LSL, 1));
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| + // Z lane.
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| + __ vmovrs(temp, EvenSRegisterOf(dvalue1));
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| + __ Lsr(temp, temp, 31);
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| + __ orr(out, out, ShifterOperand(temp, LSL, 2));
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| + // W lane.
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| + __ vmovrs(temp, OddSRegisterOf(dvalue1));
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| + __ Lsr(temp, temp, 31);
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| + __ orr(out, out, ShifterOperand(temp, LSL, 3));
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| + // Tag.
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| + __ SmiTag(out);
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| +}
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| +
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| +
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| LocationSummary* Float32x4ConstructorInstr::MakeLocationSummary() const {
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| const intptr_t kNumInputs = 4;
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| const intptr_t kNumTemps = 0;
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|