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Side by Side Diff: src/IceTargetLoweringMIPS32.h

Issue 2289043002: [SubZero] Implement lowerSwitch for MIPS (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 3 months ago
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1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
(...skipping 160 matching lines...) Expand 10 before | Expand all | Expand 10 after
171 Operand *Src1, CondMIPS32::Cond Condition) { 171 Operand *Src1, CondMIPS32::Cond Condition) {
172 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1, 172 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1,
173 Condition); 173 Condition);
174 } 174 }
175 175
176 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, 176 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0,
177 CondMIPS32::Cond Condition) { 177 CondMIPS32::Cond Condition) {
178 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Condition); 178 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Condition);
179 } 179 }
180 180
181 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0,
182 Operand *Src1, const InstMIPS32Label *Label,
183 CondMIPS32::Cond Condition) {
184 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1, Label,
185 Condition);
186 }
187
181 void _ret(Variable *RA, Variable *Src0 = nullptr) { 188 void _ret(Variable *RA, Variable *Src0 = nullptr) {
182 Context.insert<InstMIPS32Ret>(RA, Src0); 189 Context.insert<InstMIPS32Ret>(RA, Src0);
183 } 190 }
184 191
185 void _add_d(Variable *Dest, Variable *Src0, Variable *Src1) { 192 void _add_d(Variable *Dest, Variable *Src0, Variable *Src1) {
186 Context.insert<InstMIPS32Add_d>(Dest, Src0, Src1); 193 Context.insert<InstMIPS32Add_d>(Dest, Src0, Src1);
187 } 194 }
188 195
189 void _add_s(Variable *Dest, Variable *Src0, Variable *Src1) { 196 void _add_s(Variable *Dest, Variable *Src0, Variable *Src1) {
190 Context.insert<InstMIPS32Add_s>(Dest, Src0, Src1); 197 Context.insert<InstMIPS32Add_s>(Dest, Src0, Src1);
(...skipping 529 matching lines...) Expand 10 before | Expand all | Expand 10 after
720 explicit TargetHeaderMIPS32(GlobalContext *Ctx); 727 explicit TargetHeaderMIPS32(GlobalContext *Ctx);
721 728
722 private: 729 private:
723 ~TargetHeaderMIPS32() = default; 730 ~TargetHeaderMIPS32() = default;
724 }; 731 };
725 732
726 } // end of namespace MIPS32 733 } // end of namespace MIPS32
727 } // end of namespace Ice 734 } // end of namespace Ice
728 735
729 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H 736 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H
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