Add MIPS SIMD Arch (MSA) optimized MirrorRow function

source/cpu_id.cc

Index: source/cpu_id.cc
diff --git a/source/cpu_id.cc b/source/cpu_id.cc
index 84927ebc3e2b730fd637ee3519d6881c8751d556..4cb076d6ad94c33cc206194e21f74fcd1a89db81 100644
--- a/source/cpu_id.cc
+++ b/source/cpu_id.cc
@@ -259,6 +259,15 @@ int InitCpuFlags(void) {
     cpu_info &= ~kCpuHasDSPR2;
   }
 #endif
+#if defined(__mips__) && defined(__linux__)

[fbarchard1, 2016/09/14 01:48:04]

this code block can be moved inside the previous
#if defined(__mips__) && defined(__linux__)
and share the 
cpu_info |= kCpuHasMIPS;

[manojkumar.bhosale, 2016/09/14 12:45:30]

Done.

+#if defined(__mips_msa)
+  cpu_info |= kCpuHasMSA;

[fbarchard1, 2016/09/14 01:48:04]

this is a compile time test.  If built with MSA, but run on a cpu that doesnt
have it, can it be runtime detected and fall back on C code?

also note that this code current uses a constant that enables the DSPR2 code,
but that change should be in the .h

[manojkumar.bhosale, 2016/09/14 12:45:30]

Done.

+#endif
+  cpu_info |= kCpuHasMIPS;
+  if (getenv("LIBYUV_DISABLE_MSA")) {
+    cpu_info &= ~kCpuHasMSA;
+  }
+#endif
 #if defined(__arm__) || defined(__aarch64__)
 // gcc -mfpu=neon defines __ARM_NEON__
 // __ARM_NEON__ generates code that requires Neon.  NaCL also requires Neon.