Add MIPS SIMD Arch (MSA) optimized MirrorRow function

source/cpu_id.cc

 /*
  *  Copyright 2011 The LibYuv Project Authors. All rights reserved.
  *
  *  Use of this source code is governed by a BSD-style license
  *  that can be found in the LICENSE file in the root of the source
  *  tree. An additional intellectual property rights grant can be found
  *  in the file PATENTS. All contributing project authors may
  *  be found in the AUTHORS file in the root of the source tree.
  */
 
@@ skipping 143 matching lines @@
       if (p && (p[6] == ' ' || p[6] == '\n')) {
         fclose(f);
         return kCpuHasNEON;
       }
     }
   }
   fclose(f);
   return 0;
 }
 
+LIBYUV_API SAFEBUFFERS
+int MipsCpuCaps(const char* cpuinfo_name, const char ase[]) {
+  char cpuinfo_line[512];
+  int len = strlen(ase);
+  FILE* f = fopen(cpuinfo_name, "r");
+  if (!f) {
+    // ase enabled if /proc/cpuinfo is unavailable.
+    if(!strcmp(ase, " dspr2")) {
+      return kCpuHasDSPR2;
+    }
+    if(!strcmp(ase, " msa")) {

[fbarchard1, 2016/09/17 01:01:30]

if a cpu had both dspr2 and msa, the early return above would prevent msa from
being detected.  As an easy fix, suggest reversing the order, so MSA is
preferred.

[manojkumar.bhosale, 2016/09/19 08:07:21]

The 'ase' argument to the function will be either " dspr2" or " msa". So only
that string shall be compared ignoring other.
As of now used this function only for msa but separate call can be used for
dspr2 under #if defined(__mips_dspr2) at line 287.
Reversed order and strcmp check

+      return kCpuHasMSA;
+    }
+  }
+  while (fgets(cpuinfo_line, sizeof(cpuinfo_line) - 1, f)) {
+    if (memcmp(cpuinfo_line, "ASEs implemented", 16) == 0) {
+      char* p = strstr(cpuinfo_line, ase);
+      if (p && (p[len] == ' ' || p[len] == '\n')) {
+        fclose(f);
+        if(!strcmp(ase, " dspr2")) {
+          return kCpuHasDSPR2;
+        }
+        if(!strcmp(ase, " msa")) {
+          return kCpuHasMSA;
+        }
+      }
+    }
+  }
+  fclose(f);
+  return 0;
+}
+
 // CPU detect function for SIMD instruction sets.
 LIBYUV_API
 int cpu_info_ = 0;  // cpu_info is not initialized yet.
 
 // Test environment variable for disabling CPU features. Any non-zero value
 // to disable. Zero ignored to make it easy to set the variable on/off.
 #if !defined(__native_client__) && !defined(_M_ARM)
 
 static LIBYUV_BOOL TestEnv(const char* name) {
   const char* var = getenv(name);
@@ skipping 73 matching lines @@
     cpu_info &= ~kCpuHasFMA3;
   }
   if (TestEnv("LIBYUV_DISABLE_AVX3")) {
     cpu_info &= ~kCpuHasAVX3;
   }
 #endif
 #if defined(__mips__) && defined(__linux__)
 #if defined(__mips_dspr2)
   cpu_info |= kCpuHasDSPR2;
 #endif
+#if defined(__mips_msa)
+  cpu_info = MipsCpuCaps("/proc/cpuinfo", " msa");
+#endif
   cpu_info |= kCpuHasMIPS;
   if (getenv("LIBYUV_DISABLE_DSPR2")) {
     cpu_info &= ~kCpuHasDSPR2;
   }
+  if (getenv("LIBYUV_DISABLE_MSA")) {
+    cpu_info &= ~kCpuHasMSA;
+  }
 #endif
 #if defined(__arm__) || defined(__aarch64__)
 // gcc -mfpu=neon defines __ARM_NEON__
 // __ARM_NEON__ generates code that requires Neon.  NaCL also requires Neon.
 // For Linux, /proc/cpuinfo can be tested but without that assume Neon.
 #if defined(__ARM_NEON__) || defined(__native_client__) || !defined(__linux__)
   cpu_info = kCpuHasNEON;
 // For aarch64(arm64), /proc/cpuinfo's feature is not complete, e.g. no neon
 // flag in it.
 // So for aarch64, neon enabling is hard coded here.
@@ skipping 20 matching lines @@
 // Note that use of this function is not thread safe.
 LIBYUV_API
 void MaskCpuFlags(int enable_flags) {
   cpu_info_ = InitCpuFlags() & enable_flags;
 }
 
 #ifdef __cplusplus
 }  // extern "C"
 }  // namespace libyuv
 #endif