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Side by Side Diff: include/libyuv/macros_msa.h

Issue 2285683002: Add MIPS SIMD Arch (MSA) optimized MirrorRow function (Closed)
Patch Set: Fixed merge conflicts with master Created 4 years, 2 months ago
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1 /*
2 * Copyright 2016 The LibYuv Project Authors. All rights reserved.
3 *
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
9 */
10
11 #ifndef __MACROS_MSA_H__
12 #define __MACROS_MSA_H__
13
14 #if !defined(LIBYUV_DISABLE_MSA) && defined(__mips_msa)
15 #include <stdint.h>
16 #include <msa.h>
17
18 #define LD_B(RTYPE, psrc) *((RTYPE*)(psrc))
19 #define LD_UB(...) LD_B(v16u8, __VA_ARGS__)
20
21 #define ST_B(RTYPE, in, pdst) *((RTYPE*)(pdst)) = (in)
22 #define ST_UB(...) ST_B(v16u8, __VA_ARGS__)
23
24 /* Description : Load two vectors with 16 'byte' sized elements
25 Arguments : Inputs - psrc, stride
26 Outputs - out0, out1
27 Return Type - as per RTYPE
28 Details : Load 16 byte elements in 'out0' from (psrc)
29 Load 16 byte elements in 'out1' from (psrc + stride)
30 */
31 #define LD_B2(RTYPE, psrc, stride, out0, out1) { \
32 out0 = LD_B(RTYPE, (psrc)); \
33 out1 = LD_B(RTYPE, (psrc) + stride); \
34 }
35 #define LD_UB2(...) LD_B2(v16u8, __VA_ARGS__)
36 #define LD_SB2(...) LD_B2(v16i8, __VA_ARGS__)
37
38 #define LD_B4(RTYPE, psrc, stride, out0, out1, out2, out3) { \
39 LD_B2(RTYPE, (psrc), stride, out0, out1); \
40 LD_B2(RTYPE, (psrc) + 2 * stride , stride, out2, out3); \
41 }
42 #define LD_UB4(...) LD_B4(v16u8, __VA_ARGS__)
43 #define LD_SB4(...) LD_B4(v16i8, __VA_ARGS__)
44
45 /* Description : Store two vectors with stride each having 16 'byte' sized
46 elements
47 Arguments : Inputs - in0, in1, pdst, stride
48 Details : Store 16 byte elements from 'in0' to (pdst)
49 Store 16 byte elements from 'in1' to (pdst + stride)
50 */
51 #define ST_B2(RTYPE, in0, in1, pdst, stride) { \
52 ST_B(RTYPE, in0, (pdst)); \
53 ST_B(RTYPE, in1, (pdst) + stride); \
54 }
55 #define ST_UB2(...) ST_B2(v16u8, __VA_ARGS__)
56 #define ST_SB2(...) ST_B2(v16i8, __VA_ARGS__)
57
58 #define ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride) { \
59 ST_B2(RTYPE, in0, in1, (pdst), stride); \
60 ST_B2(RTYPE, in2, in3, (pdst) + 2 * stride, stride); \
61 }
62 #define ST_UB4(...) ST_B4(v16u8, __VA_ARGS__)
63 #define ST_SB4(...) ST_B4(v16i8, __VA_ARGS__)
64
65 /* Description : Shuffle byte vector elements as per mask vector
66 Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
67 Outputs - out0, out1
68 Return Type - as per RTYPE
69 Details : Byte elements from 'in0' & 'in1' are copied selectively to
70 'out0' as per control vector 'mask0'
71 */
72 #define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) { \
73 out0 = (RTYPE) __msa_vshf_b((v16i8) mask0, (v16i8) in1, (v16i8) in0); \
74 out1 = (RTYPE) __msa_vshf_b((v16i8) mask1, (v16i8) in3, (v16i8) in2); \
75 }
76 #define VSHF_B2_UB(...) VSHF_B2(v16u8, __VA_ARGS__)
77 #endif /* !defined(LIBYUV_DISABLE_MSA) && defined(__mips_msa) */
78 #endif /* __MACROS_MSA_H__ */
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