Adds ldr and str to arm64.

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM64_H_
 #define VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 29 matching lines @@
   R25 = 25,  // IP0
   R26 = 26,  // IP1
   R27 = 27,  // PP
   R28 = 28,  // CTX
   R29 = 29,  // FP
   R30 = 30,  // LR
   R31 = 31,  // ZR, SP
   kNumberOfCpuRegisters = 32,
   kNoRegister = -1,
 
+  // These registers both use the encoding R31, but to avoid mistakes we give
+  // them different values, and then translate before encoding.
+  SP = 32,
+  ZR = 33,
+
   // Aliases.
   IP0 = R25,
   IP1 = R26,
   FP = R29,
   LR = R30,
-
-  // Left abstract so we can avoid misuse.
-  SP,
-  ZR,
 };
 
 enum VRegister {
   V0  =  0,
   V1  =  1,
   V2  =  2,
   V3  =  3,
   V4  =  4,
   V5  =  5,
   V6  =  6,
@@ skipping 138 matching lines @@
   kUnsignedByte,
   kHalfword,
   kUnsignedHalfword,
   kWord,
   kUnsignedWord,
   kDoubleWord,
   kSWord,
   kDWord,
 };
 
+static inline int Log2OperandSizeBytes(OperandSize os) {
+  switch (os) {
+    case kByte:
+    case kUnsignedByte:
+      return 0;
+    case kHalfword:
+    case kUnsignedHalfword:
+      return 1;
+    case kWord:
+    case kUnsignedWord:
+    case kSWord:
+      return 2;
+    case kDoubleWord:
+    case kDWord:
+      return 3;
+    default:
+      UNREACHABLE();
+      break;
+  }
+  return -1;
+}
+
 // Opcodes from C3
 // C3.1.
 enum MainOp {
   DPImmediateMask = 0x1c000000,
   DPImmediateFixed = B28,
 
   CompareBranchMask = 0x1c000000,
   CompareBranchFixed = B28 | B26,
 
   LoadStoreMask = B27 | B25,
@@ skipping 27 matching lines @@
 
 // C3.2.7
 enum UnconditionalBranchRegOp {
   UnconditionalBranchRegMask = 0xfe000000,
   UnconditionalBranchRegFixed = CompareBranchFixed | B31 | B30 | B25,
   BR = UnconditionalBranchRegFixed | B20 | B19 | B18 | B17 | B16,
   BLR = BR | B21,
   RET = BR | B22,
 };
 
+enum LoadStoreRegOp {
+  LoadStoreRegMask = 0x3a000000,
+  LoadStoreRegFixed = LoadStoreFixed | B29 | B28,
+  STR = LoadStoreRegFixed,
+  LDR = LoadStoreRegFixed | B22,
+};
+
 // C3.4.1
 enum AddSubImmOp {
   AddSubImmMask = 0x1f000000,
   AddSubImmFixed = DPImmediateFixed | B24,
   ADDI = AddSubImmFixed,
   SUBI = AddSubImmFixed | B30,
 };
 
 // C3.4.5
 enum MoveWideOp {
@@ skipping 15 matching lines @@
 
 #define APPLY_OP_LIST(_V)                                                      \
 _V(DPImmediate)                                                                \
 _V(CompareBranch)                                                              \
 _V(LoadStore)                                                                  \
 _V(DPRegister)                                                                 \
 _V(DPSimd1)                                                                    \
 _V(DPSimd2)                                                                    \
 _V(ExceptionGen)                                                               \
 _V(System)                                                                     \
+_V(LoadStoreReg)                                                               \
 _V(UnconditionalBranchReg)                                                     \
 _V(AddSubImm)                                                                  \
 _V(MoveWide)                                                                   \
 _V(AddSubShiftExt)                                                             \
 
 
 enum Shift {
   kNoShift = -1,
   LSL = 0,  // Logical shift left
   LSR = 1,  // Logical shift right
@@ skipping 25 matching lines @@
 // instructions. Based on the "Figure 3-1 ARM instruction set summary".
 enum InstructionFields {
   // S-bit (modify condition register)
   kSShift = 29,
   kSBits = 1,
 
   // sf field.
   kSFShift = 31,
   kSFBits = 1,
 
+  // size field,
+  kSzShift = 30,
+  kSzBits = 2,
+
   // Registers.
   kRdShift = 0,
   kRdBits = 5,
   kRnShift = 5,
   kRnBits = 5,
   kRaShift = 10,
   kRaBits = 5,
   kRmShift = 16,
   kRmBits = 5,
+  kRtShift = 0,
+  kRtBits = 5,
 
   // Immediates.
   kImm3Shift = 10,
   kImm3Bits = 3,
   kImm6Shift = 10,
   kImm6Bits = 6,
+  kImm9Shift = 12,
+  kImm9Bits = 9,
   kImm12Shift = 10,
   kImm12Bits = 12,
   kImm12ShiftShift = 22,
   kImm12ShiftBits = 2,
   kImm16Shift = 5,
   kImm16Bits = 16,
 
   kHWShift = 21,
   kHWBits = 2,
 
@@ skipping 58 matching lines @@
   }
 
   // Read a bit field out of the instruction bits.
   inline int Bits(int shift, int count) const {
     return (InstructionBits() >> shift) & ((1 << count) - 1);
   }
 
 
   inline int SField() const { return Bit(kSShift); }
   inline int SFField() const { return Bit(kSFShift); }
+  inline int SzField() const { return Bits(kSzShift, kSzBits); }
   inline Register RdField() const { return static_cast<Register>(
                                         Bits(kRdShift, kRdBits)); }
   inline Register RnField() const { return static_cast<Register>(
                                         Bits(kRnShift, kRnBits)); }
   inline Register RaField() const { return static_cast<Register>(
                                         Bits(kRaShift, kRaBits)); }
   inline Register RmField() const { return static_cast<Register>(
                                         Bits(kRmShift, kRmBits)); }
+  inline Register RtField() const { return static_cast<Register>(
+                                        Bits(kRtShift, kRtBits)); }
 
   // Immediates
   inline int Imm3Field() const { return Bits(kImm3Shift, kImm3Bits); }
   inline int Imm6Field() const { return Bits(kImm6Shift, kImm6Bits); }
+  inline int Imm9Field() const { return Bits(kImm9Shift, kImm9Bits); }
+  // Sign-extended Imm9Field()
+  inline int64_t SImm9Field() const {
+      return (static_cast<int32_t>(Imm9Field()) << 23) >> 23; }
   inline int Imm12Field() const { return Bits(kImm12Shift, kImm12Bits); }
   inline int Imm16Field() const { return Bits(kImm16Shift, kImm16Bits); }
 
   inline int Imm12ShiftField() const {
     return Bits(kImm12ShiftShift, kImm12ShiftBits); }
   inline int HWField() const { return Bits(kHWShift, kHWBits); }
 
   // Shift and Extend.
   inline bool IsShift() const { return (Bit(kShiftExtendShift) == 0); }
   inline bool IsExtend() const { return (Bit(kShiftExtendShift) == 1); }
@@ skipping 55 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM64_H_