OLD | NEW |
1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <stdarg.h> | 5 #include <stdarg.h> |
6 #include <stdlib.h> | 6 #include <stdlib.h> |
7 #include <cmath> | 7 #include <cmath> |
8 | 8 |
9 #if V8_TARGET_ARCH_ARM | 9 #if V8_TARGET_ARCH_ARM |
10 | 10 |
(...skipping 3888 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3899 case 0x3: // vrintm - floor | 3899 case 0x3: // vrintm - floor |
3900 sd_value = floorf(sm_value); | 3900 sd_value = floorf(sm_value); |
3901 break; | 3901 break; |
3902 default: | 3902 default: |
3903 UNREACHABLE(); // Case analysis is exhaustive. | 3903 UNREACHABLE(); // Case analysis is exhaustive. |
3904 break; | 3904 break; |
3905 } | 3905 } |
3906 sd_value = canonicalizeNaN(sd_value); | 3906 sd_value = canonicalizeNaN(sd_value); |
3907 set_s_register_from_float(d, sd_value); | 3907 set_s_register_from_float(d, sd_value); |
3908 } | 3908 } |
| 3909 } else if ((instr->Opc1Value() == 0x4) && (instr->Bits(11, 9) == 0x5) && |
| 3910 (instr->Bit(4) == 0x0)) { |
| 3911 if (instr->SzValue() == 0x1) { |
| 3912 int m = instr->VFPMRegValue(kDoublePrecision); |
| 3913 int n = instr->VFPNRegValue(kDoublePrecision); |
| 3914 int d = instr->VFPDRegValue(kDoublePrecision); |
| 3915 double dn_value = get_double_from_d_register(n); |
| 3916 double dm_value = get_double_from_d_register(m); |
| 3917 double dd_value; |
| 3918 if (instr->Bit(6) == 0x1) { // vminnm |
| 3919 if ((dn_value < dm_value) || std::isnan(dm_value)) { |
| 3920 dd_value = dn_value; |
| 3921 } else if ((dm_value < dn_value) || std::isnan(dn_value)) { |
| 3922 dd_value = dm_value; |
| 3923 } else { |
| 3924 DCHECK_EQ(dn_value, dm_value); |
| 3925 // Make sure that we pick the most negative sign for +/-0. |
| 3926 dd_value = std::signbit(dn_value) ? dn_value : dm_value; |
| 3927 } |
| 3928 } else { // vmaxnm |
| 3929 if ((dn_value > dm_value) || std::isnan(dm_value)) { |
| 3930 dd_value = dn_value; |
| 3931 } else if ((dm_value > dn_value) || std::isnan(dn_value)) { |
| 3932 dd_value = dm_value; |
| 3933 } else { |
| 3934 DCHECK_EQ(dn_value, dm_value); |
| 3935 // Make sure that we pick the most positive sign for +/-0. |
| 3936 dd_value = std::signbit(dn_value) ? dm_value : dn_value; |
| 3937 } |
| 3938 } |
| 3939 dd_value = canonicalizeNaN(dd_value); |
| 3940 set_d_register_from_double(d, dd_value); |
| 3941 } else { |
| 3942 int m = instr->VFPMRegValue(kSinglePrecision); |
| 3943 int n = instr->VFPNRegValue(kSinglePrecision); |
| 3944 int d = instr->VFPDRegValue(kSinglePrecision); |
| 3945 float sn_value = get_float_from_s_register(n); |
| 3946 float sm_value = get_float_from_s_register(m); |
| 3947 float sd_value; |
| 3948 if (instr->Bit(6) == 0x1) { // vminnm |
| 3949 if ((sn_value < sm_value) || std::isnan(sm_value)) { |
| 3950 sd_value = sn_value; |
| 3951 } else if ((sm_value < sn_value) || std::isnan(sn_value)) { |
| 3952 sd_value = sm_value; |
| 3953 } else { |
| 3954 DCHECK_EQ(sn_value, sm_value); |
| 3955 // Make sure that we pick the most negative sign for +/-0. |
| 3956 sd_value = std::signbit(sn_value) ? sn_value : sm_value; |
| 3957 } |
| 3958 } else { // vmaxnm |
| 3959 if ((sn_value > sm_value) || std::isnan(sm_value)) { |
| 3960 sd_value = sn_value; |
| 3961 } else if ((sm_value > sn_value) || std::isnan(sn_value)) { |
| 3962 sd_value = sm_value; |
| 3963 } else { |
| 3964 DCHECK_EQ(sn_value, sm_value); |
| 3965 // Make sure that we pick the most positive sign for +/-0. |
| 3966 sd_value = std::signbit(sn_value) ? sm_value : sn_value; |
| 3967 } |
| 3968 } |
| 3969 sd_value = canonicalizeNaN(sd_value); |
| 3970 set_s_register_from_float(d, sd_value); |
| 3971 } |
3909 } else { | 3972 } else { |
3910 UNIMPLEMENTED(); | 3973 UNIMPLEMENTED(); |
3911 } | 3974 } |
3912 break; | 3975 break; |
3913 case 0x1C: | 3976 case 0x1C: |
3914 if ((instr->Bits(11, 9) == 0x5) && (instr->Bit(6) == 0) && | 3977 if ((instr->Bits(11, 9) == 0x5) && (instr->Bit(6) == 0) && |
3915 (instr->Bit(4) == 0)) { | 3978 (instr->Bit(4) == 0)) { |
3916 // VSEL* (floating-point) | 3979 // VSEL* (floating-point) |
3917 bool condition_holds; | 3980 bool condition_holds; |
3918 switch (instr->Bits(21, 20)) { | 3981 switch (instr->Bits(21, 20)) { |
(...skipping 278 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4197 set_register(sp, current_sp + sizeof(uintptr_t)); | 4260 set_register(sp, current_sp + sizeof(uintptr_t)); |
4198 return address; | 4261 return address; |
4199 } | 4262 } |
4200 | 4263 |
4201 } // namespace internal | 4264 } // namespace internal |
4202 } // namespace v8 | 4265 } // namespace v8 |
4203 | 4266 |
4204 #endif // USE_SIMULATOR | 4267 #endif // USE_SIMULATOR |
4205 | 4268 |
4206 #endif // V8_TARGET_ARCH_ARM | 4269 #endif // V8_TARGET_ARCH_ARM |
OLD | NEW |