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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2091 // Subtract Logical Register-Register-Register (64) | 2091 // Subtract Logical Register-Register-Register (64) |
2092 void Assembler::slgrk(Register r1, Register r2, Register r3) { | 2092 void Assembler::slgrk(Register r1, Register r2, Register r3) { |
2093 rrf1_form(SLGRK, r1, r2, r3); | 2093 rrf1_form(SLGRK, r1, r2, r3); |
2094 } | 2094 } |
2095 | 2095 |
2096 // ---------------------------- | 2096 // ---------------------------- |
2097 // 32-bit Multiply Instructions | 2097 // 32-bit Multiply Instructions |
2098 // ---------------------------- | 2098 // ---------------------------- |
2099 // Multiply Register-Storage (64<32) | 2099 // Multiply Register-Storage (64<32) |
2100 void Assembler::m(Register r1, const MemOperand& opnd) { | 2100 void Assembler::m(Register r1, const MemOperand& opnd) { |
| 2101 DCHECK(r1.code() % 2 == 0); |
2101 rx_form(M, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2102 rx_form(M, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2102 } | 2103 } |
2103 | 2104 |
| 2105 void Assembler::mfy(Register r1, const MemOperand& opnd) { |
| 2106 DCHECK(r1.code() % 2 == 0); |
| 2107 rxy_form(MFY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
| 2108 } |
| 2109 |
2104 // Multiply Register (64<32) | 2110 // Multiply Register (64<32) |
2105 void Assembler::mr_z(Register r1, Register r2) { | 2111 void Assembler::mr_z(Register r1, Register r2) { |
2106 DCHECK(r1.code() % 2 == 0); | 2112 DCHECK(r1.code() % 2 == 0); |
2107 rr_form(MR, r1, r2); | 2113 rr_form(MR, r1, r2); |
2108 } | 2114 } |
2109 | 2115 |
2110 // Multiply Logical Register-Storage (64<32) | 2116 // Multiply Logical Register-Storage (64<32) |
2111 void Assembler::ml(Register r1, const MemOperand& opnd) { | 2117 void Assembler::ml(Register r1, const MemOperand& opnd) { |
2112 rxy_form(ML, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2118 rxy_form(ML, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2113 } | 2119 } |
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3122 SKIP_ICACHE_FLUSH); | 3128 SKIP_ICACHE_FLUSH); |
3123 } | 3129 } |
3124 | 3130 |
3125 reloc_info_writer.Write(&rinfo); | 3131 reloc_info_writer.Write(&rinfo); |
3126 } | 3132 } |
3127 } | 3133 } |
3128 | 3134 |
3129 } // namespace internal | 3135 } // namespace internal |
3130 } // namespace v8 | 3136 } // namespace v8 |
3131 #endif // V8_TARGET_ARCH_S390 | 3137 #endif // V8_TARGET_ARCH_S390 |
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