DBC: Fixes typed data bugs. Adds unboxed int32 instructions

runtime/vm/constants_dbc.h

 // Copyright (c) 2016, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_DBC_H_
 #define VM_CONSTANTS_DBC_H_
 
 #include "platform/globals.h"
 #include "platform/assert.h"
 #include "platform/utils.h"
@@ skipping 179 matching lines @@
 //    instruction (which implements a slow path fallback).
 //
 //  - Add, Sub, Mul, Div, Mod, Shl, Shr rA, rB, rC
 //
 //    Arithmetic operations on Smis. FP[rA] <- FP[rB] op FP[rC].
 //    If these instructions can trigger a deoptimization, the following
 //    instruction should be Deopt. If no deoptimization should be triggered,
 //    the immediately following instruction is skipped. These instructions
 //    expect their operands to be Smis, but don't check that they are.
 //
-//  - ShrImm rA, rB, rC
+//  - ShlImm rA, rB, rC
 //
-//    FP[rA] <- FP[rB] >> rC. Shifts the Smi in FP[rB] right by rC. rC is
-//    assumed to be a legal positive number by which righ-shifting is possible.
+//    FP[rA] <- FP[rB] << rC. Shifts the Smi in FP[rB] left by rC. rC is
+//    assumed to be a legal positive number by which left-shifting is possible.
 //
 //  - Min, Max rA, rB, rC
 //
 //    FP[rA] <- {min, max}(FP[rB], FP[rC]). Assumes that FP[rB], and FP[rC] are
 //    Smis.
 //
 //  - Neg rA , rD
 //
 //    FP[rA] <- -FP[rD]. Assumes FP[rD] is a Smi. If there is no overflow the
 //    immediately following instruction is skipped.
@@ skipping 22 matching lines @@
 //  - UnboxDouble rA, rD
 //
 //    Unbox the double in FP[rD] into FP[rA]. Assumes FP[rD] is a double.
 //
 //  - CheckedUnboxDouble rA, rD
 //
 //    Unboxes FP[rD] into FP[rA] and skips the following instruction unless
 //    FP[rD] is not a double or a Smi. When FP[rD] is a Smi, converts it to a
 //    double.
 //
+//  - UnboxInt32 rA, rB, C
+//
+//    Unboxes the integer in FP[rB] into FP[rA]. If C == 1, the value may be
+//    truncated. If FP[rA] is successfully unboxed the following instruction is
+//    skipped.
+//
+//  - BoxInt32 rA, rD
+//
+//    Boxes the unboxed signed 32-bit integer in FP[rD] into FP[rA].
+//
+//  - BoxUint32 rA, rD
+//
+//    Boxes the unboxed unsigned 32-bit integer in FP[rD] into FP[rA].
+//
 //  - SmiToDouble rA, rD
 //
 //    Convert the Smi in FP[rD] to an unboxed double in FP[rA].
 //
 //  - DoubleToSmi rA, rD
 //
 //    If the unboxed double in FP[rD] can be converted to a Smi in FP[rA], then
 //    this instruction does so, and skips the following instruction. Otherwise,
 //    the following instruction is not skipped.
 //
@@ skipping 344 matching lines @@
   V(EqualTOS,                        0, ___, ___, ___) \
   V(LessThanTOS,                     0, ___, ___, ___) \
   V(GreaterThanTOS,                  0, ___, ___, ___) \
   V(Add,                         A_B_C, reg, reg, reg) \
   V(Sub,                         A_B_C, reg, reg, reg) \
   V(Mul,                         A_B_C, reg, reg, reg) \
   V(Div,                         A_B_C, reg, reg, reg) \
   V(Mod,                         A_B_C, reg, reg, reg) \
   V(Shl,                         A_B_C, reg, reg, reg) \
   V(Shr,                         A_B_C, reg, reg, reg) \
-  V(ShrImm,                      A_B_C, reg, reg, num) \
+  V(ShlImm,                      A_B_C, reg, reg, num) \
   V(Neg,                           A_D, reg, reg, ___) \
   V(BitOr,                       A_B_C, reg, reg, reg) \
   V(BitAnd,                      A_B_C, reg, reg, reg) \
   V(BitXor,                      A_B_C, reg, reg, reg) \
   V(BitNot,                        A_D, reg, reg, ___) \
   V(Min,                         A_B_C, reg, reg, reg) \
   V(Max,                         A_B_C, reg, reg, reg) \
   V(WriteIntoDouble,               A_D, reg, reg, ___) \
   V(UnboxDouble,                   A_D, reg, reg, ___) \
   V(CheckedUnboxDouble,            A_D, reg, reg, ___) \
+  V(UnboxInt32,                  A_B_C, reg, reg, num) \
+  V(BoxInt32,                      A_D, reg, reg, ___) \
+  V(BoxUint32,                     A_D, reg, reg, ___) \
   V(SmiToDouble,                   A_D, reg, reg, ___) \
   V(DoubleToSmi,                   A_D, reg, reg, ___) \
   V(DAdd,                        A_B_C, reg, reg, reg) \
   V(DSub,                        A_B_C, reg, reg, reg) \
   V(DMul,                        A_B_C, reg, reg, reg) \
   V(DDiv,                        A_B_C, reg, reg, reg) \
   V(DNeg,                          A_D, reg, reg, ___) \
   V(DSqrt,                         A_D, reg, reg, ___) \
   V(DMin,                        A_B_C, reg, reg, reg) \
   V(DMax,                        A_B_C, reg, reg, reg) \
@@ skipping 28 matching lines @@
   V(IfEqStrictNum,                 A_D, reg, reg, ___) \
   V(IfEqNull,                        A, reg, ___, ___) \
   V(IfNeNull,                        A, reg, ___, ___) \
   V(CreateArrayTOS,                  0, ___, ___, ___) \
   V(Allocate,                        D, lit, ___, ___) \
   V(AllocateT,                       0, ___, ___, ___) \
   V(StoreIndexedTOS,                 0, ___, ___, ___) \
   V(StoreIndexed,                A_B_C, reg, reg, reg) \
   V(StoreIndexedUint8,           A_B_C, reg, reg, reg) \
   V(StoreIndexedExternalUint8,   A_B_C, reg, reg, reg) \
+  V(StoreIndexedUint32,          A_B_C, reg, reg, reg) \
   V(StoreIndexedFloat64,         A_B_C, reg, reg, reg) \
   V(LoadIndexed,                 A_B_C, reg, reg, reg) \
   V(LoadIndexedUint8,            A_B_C, reg, reg, reg) \
   V(LoadIndexedInt8,             A_B_C, reg, reg, reg) \
+  V(LoadIndexedInt32,            A_B_C, reg, reg, reg) \
+  V(LoadIndexedUint32,           A_B_C, reg, reg, reg) \
   V(LoadIndexedExternalUint8,    A_B_C, reg, reg, reg) \
   V(LoadIndexedExternalInt8,     A_B_C, reg, reg, reg) \
   V(LoadIndexedFloat64,          A_B_C, reg, reg, reg) \
   V(LoadIndexedOneByteString,    A_B_C, reg, reg, reg) \
   V(LoadIndexedTwoByteString,    A_B_C, reg, reg, reg) \
   V(StoreField,                  A_B_C, reg, num, reg) \
   V(StoreFieldTOS,                   D, num, ___, ___) \
   V(LoadField,                   A_B_C, reg, reg, num) \
   V(LoadUntagged,                A_B_C, reg, reg, num) \
   V(LoadFieldTOS,                    D, num, ___, ___) \
@@ skipping 161 matching lines @@
 
 // After a comparison, the condition NEXT_IS_TRUE means the following
 // instruction is executed if the comparision is true and skipped over overwise.
 // Conidition NEXT_IS_FALSE means the following instruction is executed if the
 // comparison is false and skipped over otherwise.
 enum Condition { NEXT_IS_TRUE, NEXT_IS_FALSE };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_DBC_H_