[turbofan] Add Float32(Max|Min) machine operators.

src/compiler/arm/code-generator-arm.cc

Index: src/compiler/arm/code-generator-arm.cc
diff --git a/src/compiler/arm/code-generator-arm.cc b/src/compiler/arm/code-generator-arm.cc
index fdddb684495c435e7180da45e33ae83f4f000419..b8a4b080a93678b10d3502af14150e78ae276781 100644
--- a/src/compiler/arm/code-generator-arm.cc
+++ b/src/compiler/arm/code-generator-arm.cc
@@ -1379,6 +1379,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vstr(i.InputDoubleRegister(0), i.InputOffset(1));
       DCHECK_EQ(LeaveCC, i.OutputSBit());
       break;
+    case kArmFloat32Max: {
+      FloatRegister left_reg = i.InputFloat32Register(0);
+      FloatRegister right_reg = i.InputFloat32Register(1);
+      FloatRegister result_reg = i.OutputFloat32Register();
+      Label result_is_nan, return_left, return_right, check_zero, done;
+      __ VFPCompareAndSetFlags(left_reg, right_reg);
+      __ b(mi, &return_right);
+      __ b(gt, &return_left);
+      __ b(vs, &result_is_nan);
+      // Left equals right => check for -0.
+      __ VFPCompareAndSetFlags(left_reg, 0.0);
+      if (left_reg.is(result_reg) || right_reg.is(result_reg)) {
+        __ b(ne, &done);  // left == right != 0.
+      } else {
+        __ b(ne, &return_left);  // left == right != 0.
+      }
+      // At this point, both left and right are either 0 or -0.
+      // Since we operate on +0 and/or -0, vadd and vand have the same effect;
+      // the decision for vadd is easy because vand is a NEON instruction.
+      __ vadd(result_reg, left_reg, right_reg);
+      __ b(&done);
+      __ bind(&result_is_nan);
+      __ vadd(result_reg, left_reg, right_reg);
+      __ b(&done);
+      __ bind(&return_right);
+      __ Move(result_reg, right_reg);
+      if (!left_reg.is(result_reg)) __ b(&done);
+      __ bind(&return_left);
+      __ Move(result_reg, left_reg);
+      __ bind(&done);
+      break;
+    }
     case kArmFloat64Max: {
       DwVfpRegister left_reg = i.InputDoubleRegister(0);
       DwVfpRegister right_reg = i.InputDoubleRegister(1);
@@ -1411,6 +1443,45 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ bind(&done);
       break;
     }
+    case kArmFloat32Min: {
+      FloatRegister left_reg = i.InputFloat32Register(0);
+      FloatRegister right_reg = i.InputFloat32Register(1);
+      FloatRegister result_reg = i.OutputFloat32Register();
+      Label result_is_nan, return_left, return_right, check_zero, done;
+      __ VFPCompareAndSetFlags(left_reg, right_reg);
+      __ b(mi, &return_left);
+      __ b(gt, &return_right);
+      __ b(vs, &result_is_nan);
+      // Left equals right => check for -0.
+      __ VFPCompareAndSetFlags(left_reg, 0.0);
+      if (left_reg.is(result_reg) || right_reg.is(result_reg)) {
+        __ b(ne, &done);  // left == right != 0.
+      } else {
+        __ b(ne, &return_left);  // left == right != 0.
+      }
+      // At this point, both left and right are either 0 or -0.
+      // We could use a single 'vorr' instruction here if we had NEON support.
+      // The algorithm is: -((-L) + (-R)), which in case of L and R being
+      // different registers is most efficiently expressed as -((-L) - R).
+      __ vneg(left_reg, left_reg);
+      if (left_reg.is(right_reg)) {
+        __ vadd(result_reg, left_reg, right_reg);
+      } else {
+        __ vsub(result_reg, left_reg, right_reg);
+      }
+      __ vneg(result_reg, result_reg);
+      __ b(&done);
+      __ bind(&result_is_nan);
+      __ vadd(result_reg, left_reg, right_reg);
+      __ b(&done);
+      __ bind(&return_right);
+      __ Move(result_reg, right_reg);
+      if (!left_reg.is(result_reg)) __ b(&done);
+      __ bind(&return_left);
+      __ Move(result_reg, left_reg);
+      __ bind(&done);
+      break;
+    }
     case kArmFloat64Min: {
       DwVfpRegister left_reg = i.InputDoubleRegister(0);
       DwVfpRegister right_reg = i.InputDoubleRegister(1);